diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index b912c518c..2f3dd892f 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -52,6 +52,7 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx, fpga_fabric_verilog(openfpga_ctx.mutable_module_graph(), openfpga_ctx.mutable_verilog_netlists(), + openfpga_ctx.blwl_shift_register_banks(), openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), openfpga_ctx.decoder_lib(), diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp index b22de5920..8ac019781 100644 --- a/openfpga/src/fpga_verilog/verilog_api.cpp +++ b/openfpga/src/fpga_verilog/verilog_api.cpp @@ -55,6 +55,7 @@ namespace openfpga { ********************************************************************/ void fpga_fabric_verilog(ModuleManager &module_manager, NetlistManager &netlist_manager, + const std::array& blwl_sr_banks, const CircuitLibrary &circuit_lib, const MuxLibrary &mux_lib, const DecoderLibrary &decoder_lib, @@ -94,6 +95,7 @@ void fpga_fabric_verilog(ModuleManager &module_manager, * Without the modules in the module manager, core logic generation is not possible!!! */ print_verilog_submodule(module_manager, netlist_manager, + blwl_sr_banks, mux_lib, decoder_lib, circuit_lib, submodule_dir_path, options); diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h index 934dc08f7..ef550c76d 100644 --- a/openfpga/src/fpga_verilog/verilog_api.h +++ b/openfpga/src/fpga_verilog/verilog_api.h @@ -23,6 +23,7 @@ #include "io_location_map.h" #include "fabric_global_port_info.h" #include "vpr_netlist_annotation.h" +#include "memory_bank_shift_register_banks.h" #include "fabric_verilog_options.h" #include "verilog_testbench_options.h" @@ -35,6 +36,7 @@ namespace openfpga { void fpga_fabric_verilog(ModuleManager& module_manager, NetlistManager& netlist_manager, + const std::array& blwl_sr_banks, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const DecoderLibrary& decoder_lib, diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h index 639c1575a..3c164feee 100644 --- a/openfpga/src/fpga_verilog/verilog_constants.h +++ b/openfpga/src/fpga_verilog/verilog_constants.h @@ -26,6 +26,7 @@ constexpr char* MUXES_VERILOG_FILE_NAME = "muxes.v"; constexpr char* LOCAL_ENCODER_VERILOG_FILE_NAME = "local_encoder.v"; constexpr char* ARCH_ENCODER_VERILOG_FILE_NAME = "arch_encoder.v"; constexpr char* MEMORIES_VERILOG_FILE_NAME = "memories.v"; +constexpr char* SHIFT_REGISTER_BANKS_VERILOG_FILE_NAME = "shift_register_banks.v"; constexpr char* WIRES_VERILOG_FILE_NAME = "wires.v"; constexpr char* ESSENTIALS_VERILOG_FILE_NAME = "inv_buf_passgate.v"; constexpr char* CONFIG_PERIPHERAL_VERILOG_FILE_NAME = "config_peripherals.v"; diff --git a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp new file mode 100644 index 000000000..4d629a0cb --- /dev/null +++ b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp @@ -0,0 +1,81 @@ +/********************************************************************* + * This file includes functions to generate Verilog submodules for + * the memories that are affiliated to multiplexers and other programmable + * circuit models, such as IOPADs, LUTs, etc. + ********************************************************************/ +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" + +/* Headers from openfpgautil library */ +#include "openfpga_digest.h" + +#include "mux_graph.h" +#include "module_manager.h" +#include "circuit_library_utils.h" +#include "mux_utils.h" + +#include "openfpga_naming.h" + +#include "verilog_constants.h" +#include "verilog_writer_utils.h" +#include "verilog_module_writer.h" +#include "verilog_shift_register_banks.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/********************************************************************* + * Generate Verilog modules for + * the shift register banks that are used to control BL/WLs + ********************************************************************/ +void print_verilog_submodule_shift_register_banks(const ModuleManager& module_manager, + NetlistManager& netlist_manager, + const std::array& blwl_sr_banks, + const std::string& submodule_dir, + const FabricVerilogOption& options) { + + /* Plug in with the mux subckt */ + std::string verilog_fname(submodule_dir + std::string(SHIFT_REGISTER_BANKS_VERILOG_FILE_NAME)); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_stream(verilog_fname.c_str(), fp); + + /* Print out debugging information for if the file is not opened/created properly */ + VTR_LOG("Writing Verilog netlist for shift register banks '%s' ...", + verilog_fname.c_str()); + + print_verilog_file_header(fp, "Shift register banks used in FPGA"); + + /* Create the memory circuits for the multiplexer */ + for (const auto& sr_bank : blwl_sr_banks) { + for (const ModuleId& sr_module : sr_bank.shift_register_bank_unique_modules()) { + VTR_ASSERT(true == module_manager.valid_module_id(sr_module)); + /* Write the module content in Verilog format */ + write_verilog_module_to_file(fp, module_manager, sr_module, + options.explicit_port_mapping(), + options.default_net_type()); + + /* Add an empty line as a splitter */ + fp << std::endl; + } + } + + /* Close the file stream */ + fp.close(); + + /* Add fname to the netlist name list */ + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST); + + VTR_LOG("Done\n"); +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_shift_register_banks.h b/openfpga/src/fpga_verilog/verilog_shift_register_banks.h new file mode 100644 index 000000000..2de1bedee --- /dev/null +++ b/openfpga/src/fpga_verilog/verilog_shift_register_banks.h @@ -0,0 +1,29 @@ +#ifndef VERILOG_SHIFT_REGISTER_BANKS_H +#define VERILOG_SHIFT_REGISTER_BANKS_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include + +#include "memory_bank_shift_register_banks.h" +#include "module_manager.h" +#include "netlist_manager.h" +#include "fabric_verilog_options.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +void print_verilog_submodule_shift_register_banks(const ModuleManager& module_manager, + NetlistManager& netlist_manager, + const std::array& blwl_sr_banks, + const std::string& submodule_dir, + const FabricVerilogOption& options); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/fpga_verilog/verilog_submodule.cpp b/openfpga/src/fpga_verilog/verilog_submodule.cpp index d2bca2aa9..0cb2c97a4 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule.cpp +++ b/openfpga/src/fpga_verilog/verilog_submodule.cpp @@ -14,6 +14,7 @@ #include "verilog_lut.h" #include "verilog_wire.h" #include "verilog_memory.h" +#include "verilog_shift_register_banks.h" #include "verilog_writer_utils.h" #include "verilog_constants.h" @@ -33,6 +34,7 @@ namespace openfpga { ********************************************************************/ void print_verilog_submodule(ModuleManager& module_manager, NetlistManager& netlist_manager, + const std::array& blwl_sr_banks, const MuxLibrary& mux_lib, const DecoderLibrary& decoder_lib, const CircuitLibrary& circuit_lib, @@ -84,14 +86,22 @@ void print_verilog_submodule(ModuleManager& module_manager, submodule_dir, fpga_verilog_opts.default_net_type()); - /* 4. Memories */ + /* Memories */ print_verilog_submodule_memories(const_cast(module_manager), netlist_manager, mux_lib, circuit_lib, submodule_dir, fpga_verilog_opts); - /* 5. Dump template for all the modules */ + /* Shift register banks */ + print_verilog_submodule_shift_register_banks(const_cast(module_manager), + netlist_manager, + blwl_sr_banks, + submodule_dir, + fpga_verilog_opts); + + + /* Dump template for all the modules */ if (true == fpga_verilog_opts.print_user_defined_template()) { print_verilog_submodule_templates(const_cast(module_manager), circuit_lib, diff --git a/openfpga/src/fpga_verilog/verilog_submodule.h b/openfpga/src/fpga_verilog/verilog_submodule.h index 27bf7fdba..d25ec4844 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule.h +++ b/openfpga/src/fpga_verilog/verilog_submodule.h @@ -8,6 +8,7 @@ #include "netlist_manager.h" #include "mux_library.h" #include "decoder_library.h" +#include "memory_bank_shift_register_banks.h" #include "fabric_verilog_options.h" /******************************************************************** @@ -19,6 +20,7 @@ namespace openfpga { void print_verilog_submodule(ModuleManager& module_manager, NetlistManager& netlist_manager, + const std::array& blwl_sr_banks, const MuxLibrary& mux_lib, const DecoderLibrary& decoder_lib, const CircuitLibrary& circuit_lib,