FPGA-Verilog_doc_update

docs/source/fpga_spice/index.rst

@@ -1,3 +1,6 @@
+FPGA-SPICE: SPICE AUTO-GENERATION
+====================================
+
 .. _fpga_spice:
    User Manual for FPGA-SPICE support
  

docs/source/fpga_verilog/command_line_usage.rst

@@ -1,4 +1,25 @@
-Command-line Options for FPGA Bitstream Generator
+Command-line Options for FPGA-Verilog Generator
 =================================================
 
-**Under Construction**
+All the command line options of FPGA-Verilog can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find:
+
+FPGA-Verilog Supported Options::
+
+	--fpga_verilog
+	--fpga_verilog_dir <directory_path_of_dumped_verilog_files>
+
+.. csv-table:: Commmand-line Options of FPGA-Verilog
+   :header: "Command Options", "Description"
+   :widths: 15, 30
+
+   "--fpga_verilog", "Turn on the FPGA-Verilog."
+   "--fpga_verilog_dir <dir_path>", "Specify the directory that all the Verilog files will be outputted to. <dir_path> is the destination directory."
+
+.. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are: 
+
+	* **sub_module:** contains each module verilog file and is more detailed in the next part *Verilog Output File Format*. 
+	* **routing:** contains the Verilog routing files. 
+	* **lib:** contains the grids Verilog files.
+
+
+

docs/source/fpga_verilog/file_organization.rst

@@ -1,4 +1,86 @@
 Verilog Output File Format
 ============================
 
-**Under Construction**
+The Verilog is a description language well known by the industry. It won't be explain what is Verilog in this documentation but focus on how this generated Verilog files match previous XML description file. The Verilog files are generated by the FPGA-Verilog tool from XML description file and are structured as follow:
+
+.. code-block:: verilog
+
+  `timescale reference_time/precision_value
+
+  module name_module (
+    input [0:N] name1,
+    .
+    .
+    .
+    input nameX,
+    output [0:M] name2,
+    .
+    .
+    .
+    output nameY );
+
+    wire name;
+
+    assign name3 = name4;
+
+    submodule_name submodule_instantiation_name (
+	IO1,
+	.
+	.
+	.
+	IOZ );
+
+  endmodule;
+
+* **module name**: is the translation from *<circuit_model name="name_module"/>*. 
+
+	* **input [0:N] name1**: is the translation from *<port type="input" prefix="name1" size="N+1"/>*. 
+
+		* [0:N] is useful only if the input is a vector ( N>0 ), else it won't appear.
+		* There is as many input lines in Verilog file as in XML file.
+
+	* **output [0:M] name2**: is the translation from *<port type="output" prefix="name2" size="M+1"/>*. 
+
+		* [0:M] is useful only if the output is a vector ( M>0 ), else it won't appear.
+		* There is as many output lines in Verilog file as in XML file.
+
+* **wire name**: create a wire which could be useful for interconnections. 
+
+* **assign name3 = name4**: connect name3 and name4 wires.
+
+	* If name3 is connected only to name4, it could be translated as a *direct interconnect*
+
+		.. code-block:: xml
+
+		  <interconnect>
+		    <direct name="link" input="name3" output="name4"/> 
+		  </interconnect>
+
+	* Else, it could be translated as a *complete interconnect*:
+
+		.. code-block:: xml
+
+		  <interconnect>
+		    <complete name="link" input="name3" output="name4"/> 
+		  </interconnect>
+
+* **submodule_name**: is the module name to instantiate in the module. It's like a *circuit_model* with *circuit_model* composing it (the Multiplexer for example).
+
+	* **submodule_instantiation_name**: is a name created to differentiate many instances of a same submodule in the module. Usually, an underscore followed by a number is used ( _0 or _1 for example).
+
+	* **IO**: for each submodule IO a wire or a module IO as to be linked. IO1 is the first IO declared in the submodule definition. Example of a submodule with 4 IO:
+
+		.. code-block:: verilog
+
+		  submodule_name submodule_instantiation_name (
+		    name1,	// IO1 should be connected to module input name1
+		    nameX,	// IO2 should be connected to module input nameX
+		    name,	// IO3 should be connected to wire name3
+		    name2 );	// IO4 should be connected to module output name2
+
+
+
+
+
+
+.. note:: When Verilog netlist is provided by the user, names in Verliog file must match names in XML files.

docs/source/fpga_verilog/index.rst

@@ -1,3 +1,6 @@
+FPGA-VERILOG: VERILOG AUTO-GENERATION
+=====================================
+
 .. _fpga_verilog:
    User Manual for FPGA Verilog Generator