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[core] fixed the bug in ccff v2 on config enable signal drivers

This commit is contained in:
tangxifan 2023-11-03 10:25:12 -07:00
parent 3a8260736c
commit 2cd3453629
1 changed files with 1 additions and 1 deletions
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2
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
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@ -398,7 +398,7 @@ static void print_verilog_top_testbench_global_config_done_ports_stimuli(
module_global_port)); module_global_port));
BasicPort stimuli_config_done_port( BasicPort stimuli_config_done_port(
std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); std::string(TOP_TB_CONFIG_ALL_DONE_PORT_NAME), 1);
/* Wire the port to the input stimuli: /* Wire the port to the input stimuli:
* The wiring will be inverted if the default value of the global port is 1 * The wiring will be inverted if the default value of the global port is 1
* Otherwise, the wiring will not be inverted! * Otherwise, the wiring will not be inverted!