[test] add a new testcase to validate programmable clock network with internal drivers

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -233,6 +233,7 @@ run-task basic_tests/clock_network/homo_1clock_2layer $@
 run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@
 run-task basic_tests/clock_network/homo_2clock_2layer $@
 run-task basic_tests/clock_network/homo_1clock_1_reset_2layer $@
+run-task basic_tests/clock_network/homo_1clock_1_reset_2layer_internal_driver $@
 
 echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific";
 run-task basic_tests/verific_test $@

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml

@@ -0,0 +1,40 @@
+<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0"> 
+  <clock_network name="clk_tree_2lvl" width="1"> 
+    <spine name="clk_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
+      <switch_point tap="clk_rib_lvl1_sw0_upper" x="1" y="1"> 
+        <internal_driver tile_pin="clb.O[0:7]"/>
+      </switch_point>
+      <switch_point tap="clk_rib_lvl1_sw0_lower" x="1" y="1"> 
+        <internal_driver tile_pin="clb.O[0:7]"/>
+      </switch_point>
+      <switch_point tap="clk_rib_lvl1_sw1_upper" x="2" y="1"> 
+        <internal_driver tile_pin="clb.O[0:7]"/>
+      </switch_point>
+      <switch_point tap="clk_rib_lvl1_sw1_lower" x="2" y="1"> 
+        <internal_driver tile_pin="clb.O[0:7]"/>
+      </switch_point>
+    </spine>  
+    <spine name="clk_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
+    <spine name="clk_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
+    <spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
+    <spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
+    <taps>
+      <tap tile_pin="clb[0:0].clk[0:0]"/>
+    </taps>
+  </clock_network>  
+  <clock_network name="rst_tree_2lvl" width="1"> 
+    <spine name="rst_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
+      <switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1"/> 
+      <switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1"/> 
+      <switch_point tap="rst_rib_lvl1_sw1_upper" x="2" y="1"/> 
+      <switch_point tap="rst_rib_lvl1_sw1_lower" x="2" y="1"/> 
+    </spine>  
+    <spine name="rst_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
+    <spine name="rst_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
+    <spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
+    <spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
+    <taps>
+      <tap tile_pin="clb[0:0].reset[0:0]"/>
+    </taps>
+  </clock_network>  
+</clock_networks> 

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml

@@ -0,0 +1,7 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="reset"/>
+</pin_constraints>
+

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml

@@ -0,0 +1,7 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="resetb" default_value="1"/>
+</pin_constraints>
+

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/repack_pin_constraints.xml

@@ -0,0 +1,4 @@
+<repack_design_constraints>
+  <!-- Intended to be dummy -->
+</repack_design_constraints>
+

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf

@@ -0,0 +1,53 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 3*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=40
+openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml
+openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
+bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = counter
+bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml
+bench0_openfpga_verilog_testbench_port_mapping=
+
+bench1_top = counter
+bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml
+bench1_openfpga_verilog_testbench_port_mapping=
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=