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[FPGA-Verilog] Fixed the bug on pin constraints

This commit is contained in:
tangxifan 2022-02-13 22:08:06 -08:00
parent b1377f0d34
commit 2ca73d79e4
1 changed files with 1 additions and 1 deletions
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2
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
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@ -152,7 +152,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
BasicPort module_clock_pin(module_global_port.get_name() + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), module_global_port.pins()[pin_id], module_global_port.pins()[pin_id]);
/* If the clock port name is in the pin constraints, we should wire it to the constrained pin */
std::string constrained_net_name = pin_constraints.pin_net(module_clock_pin);
std::string constrained_net_name = pin_constraints.pin_net(BasicPort(module_global_port.get_name(), module_global_port.pins()[pin_id], module_global_port.pins()[pin_id]));
/* If constrained to an open net or there is no clock in the benchmark, we assign it to a default value */
if ( (true == pin_constraints.unmapped_net(constrained_net_name))