From 2ca73d79e4807b626ecfa3663b716c564837cab2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 13 Feb 2022 22:08:06 -0800 Subject: [PATCH] [FPGA-Verilog] Fixed the bug on pin constraints --- openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 96a6d6833..c382acf8c 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -152,7 +152,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp, BasicPort module_clock_pin(module_global_port.get_name() + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), module_global_port.pins()[pin_id], module_global_port.pins()[pin_id]); /* If the clock port name is in the pin constraints, we should wire it to the constrained pin */ - std::string constrained_net_name = pin_constraints.pin_net(module_clock_pin); + std::string constrained_net_name = pin_constraints.pin_net(BasicPort(module_global_port.get_name(), module_global_port.pins()[pin_id], module_global_port.pins()[pin_id])); /* If constrained to an open net or there is no clock in the benchmark, we assign it to a default value */ if ( (true == pin_constraints.unmapped_net(constrained_net_name))