diff --git a/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.blif b/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.blif
new file mode 100644
index 000000000..317233080
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.blif
@@ -0,0 +1,10 @@
+.model discrete_dffn
+.inputs clk_ni d_i
+.outputs d_o
+
+.names clk_ni int_clk
+0 1
+
+.subckt dff D=d_i Q=d_o C=int_clk 
+
+.end
diff --git a/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.v b/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.v
new file mode 100644
index 000000000..fce53a8cd
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.v
@@ -0,0 +1,23 @@
+/////////////////////////////////////////
+//  Functionality: A FF with inverted clk. This is useful to test if an FPGA supports clock generation internally or an FPGA supports negative-edged clock
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module discrete_dffn(
+  clk_ni,
+  d_i,
+  d_o);
+input wire clk_ni;
+input wire d_i;
+output reg d_o;
+
+wire int_clk;
+
+assign int_clk = ~clk_ni;
+
+always @(posedge int_clk) begin
+  d_o <= d_i;
+end
+
+endmodule
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_pin_constraints.xml
new file mode 100644
index 000000000..e0aeb4cd2
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_pin_constraints.xml
@@ -0,0 +1,5 @@
+<pin_constraints>
+  <!-- Intend to be dummy -->
+  <!-- set_io pin="op_clk[0]" net="clk_ni"/ -->
+</pin_constraints>
+
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_repack_design_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_repack_design_constraints.xml
new file mode 100644
index 000000000..a84216e64
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/dffn_repack_design_constraints.xml
@@ -0,0 +1,5 @@
+<repack_design_constraints>
+  <!-- pin_constraint pb_type="clb" pin="clk[0]" net="clk_ni"/ -->
+  <!-- Leave lclk unconstrained as it may be mapped to any internal clock signals -->
+</repack_design_constraints>
+
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
index 6e4b75067..5bffd2c6a 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_clk_gen/config/task.conf
@@ -13,7 +13,8 @@ power_analysis = false
 spice_output=false
 verilog_output=true
 timeout_each_job = 3*60
-fpga_flow=yosys_vpr
+#fpga_flow=yosys_vpr
+fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/local_clk_gen_example_script.openfpga
@@ -25,7 +26,8 @@ openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_con
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.blif
+#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_divider/clk_divider.v
 
 [SYNTHESIS_PARAM]
 # Yosys script parameters
@@ -35,10 +37,15 @@ bench_read_verilog_options_common = -nolatches
 bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
 bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
 
-bench0_top = clk_divider
-bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
+bench0_top = discrete_dffn
+bench0_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/discrete_dffn/discrete_dffn.v
+bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/dffn_pin_constraints.xml
+bench0_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/dffn_repack_design_constraints.xml
+
+#bench1_top = clk_divider
+#bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 # FIXME: Enable this once VPR can accept clock routing for specific clock signals
-#end_flow_with_test=
-#vpr_fpga_verilog_formal_verification_top_netlist=
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=