From 2c5634ee768f01003186b62ddf1675d0ad79928e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 13 Mar 2021 20:05:18 -0700 Subject: [PATCH] [Tool] Change pin naming of grid modules to be related to architecture port names --- .../annotation/annotate_physical_tiles.cpp | 48 +++++++++++++ .../src/annotation/annotate_physical_tiles.h | 23 ++++++ .../src/annotation/vpr_device_annotation.cpp | 52 ++++++++++++++ .../src/annotation/vpr_device_annotation.h | 15 ++++ openfpga/src/base/openfpga_link_arch.cpp | 5 ++ openfpga/src/base/openfpga_naming.cpp | 45 +++++------- openfpga/src/base/openfpga_naming.h | 12 ++-- openfpga/src/fabric/build_device_module.cpp | 1 + .../build_grid_module_duplicated_pins.cpp | 29 ++++++-- .../build_grid_module_duplicated_pins.h | 3 + .../src/fabric/build_grid_module_utils.cpp | 7 +- openfpga/src/fabric/build_grid_module_utils.h | 2 + openfpga/src/fabric/build_grid_modules.cpp | 18 ++++- openfpga/src/fabric/build_top_module.cpp | 5 +- openfpga/src/fabric/build_top_module.h | 2 + .../fabric/build_top_module_connection.cpp | 70 ++++++++++++++----- .../src/fabric/build_top_module_connection.h | 3 + .../src/fabric/build_top_module_directs.cpp | 28 ++++++-- .../src/fabric/build_top_module_directs.h | 2 + 19 files changed, 305 insertions(+), 65 deletions(-) create mode 100644 openfpga/src/annotation/annotate_physical_tiles.cpp create mode 100644 openfpga/src/annotation/annotate_physical_tiles.h diff --git a/openfpga/src/annotation/annotate_physical_tiles.cpp b/openfpga/src/annotation/annotate_physical_tiles.cpp new file mode 100644 index 000000000..4c95b0754 --- /dev/null +++ b/openfpga/src/annotation/annotate_physical_tiles.cpp @@ -0,0 +1,48 @@ +/******************************************************************** + * This file includes functions to build links between pb_types + * in particular to annotate the physical mode and physical pb_type + *******************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_time.h" +#include "vtr_assert.h" +#include "vtr_log.h" + +#include "annotate_physical_tiles.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Build the fast look-up for each physical tile between + * pin index and the physical port information, i.e., port name and port index + *******************************************************************/ +void build_physical_tile_pin2port_info(const DeviceContext& vpr_device_ctx, + VprDeviceAnnotation& vpr_device_annotation) { + + vtr::ScopedStartFinishTimer timer("Build fast look-up for physical tile pins"); + + for (const t_physical_tile_type& physical_tile : vpr_device_ctx.physical_tile_types) { + /* Count the number of pins for each sub tile */ + int num_pins_per_subtile = 0; + for (const t_physical_tile_port& tile_port : physical_tile.ports) { + num_pins_per_subtile += tile_port.num_pins; + } + /* For each sub tile, the starting pin index is (num_pins_per_subtile * index) + abs_index */ + for (int subtile_index = 0; subtile_index < physical_tile.capacity; ++subtile_index) { + for (const t_physical_tile_port& tile_port : physical_tile.ports) { + for (int pin_index = 0; pin_index < tile_port.num_pins; ++pin_index) { + int absolute_pin_index = subtile_index * num_pins_per_subtile + tile_port.absolute_first_pin_index + pin_index; + BasicPort tile_port_info(tile_port.name, pin_index, pin_index); + vpr_device_annotation.add_physical_tile_pin2port_info_pair(&physical_tile, + absolute_pin_index, + tile_port_info); + vpr_device_annotation.add_physical_tile_pin_subtile_index(&physical_tile, + absolute_pin_index, + subtile_index); + } + } + } + } +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/annotation/annotate_physical_tiles.h b/openfpga/src/annotation/annotate_physical_tiles.h new file mode 100644 index 000000000..726461359 --- /dev/null +++ b/openfpga/src/annotation/annotate_physical_tiles.h @@ -0,0 +1,23 @@ +#ifndef ANNOTATE_PHYSICAL_TILES_H +#define ANNOTATE_PHYSICAL_TILES_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "vpr_context.h" +#include "openfpga_context.h" +#include "vpr_device_annotation.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +void build_physical_tile_pin2port_info(const DeviceContext& vpr_device_ctx, + VprDeviceAnnotation& vpr_device_annotation); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/annotation/vpr_device_annotation.cpp b/openfpga/src/annotation/vpr_device_annotation.cpp index f07378634..c2eed00ab 100644 --- a/openfpga/src/annotation/vpr_device_annotation.cpp +++ b/openfpga/src/annotation/vpr_device_annotation.cpp @@ -278,6 +278,46 @@ LbRRGraph VprDeviceAnnotation::physical_lb_rr_graph(t_pb_graph_node* pb_graph_he return physical_lb_rr_graphs_.at(pb_graph_head); } +BasicPort VprDeviceAnnotation::physical_tile_pin_port_info(t_physical_tile_type_ptr physical_tile, + const int& pin_index) const { + /* Try to find the physical tile in the fast look-up */ + auto physical_tile_search_result = physical_tile_pin2port_info_map_.find(physical_tile); + if (physical_tile_search_result == physical_tile_pin2port_info_map_.end()) { + /* Not found. Return an invalid port */ + return BasicPort(); + } + + /* Try to find the physical tile port info with pin index */ + auto pin_search_result = physical_tile_search_result->second.find(pin_index); + if (pin_search_result == physical_tile_search_result->second.end()) { + /* Not found. Return an invalid port */ + return BasicPort(); + } + + /* Reach here, we should find a port. Return the port information */ + return pin_search_result->second; +} + +int VprDeviceAnnotation::physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile, + const int& pin_index) const { + /* Try to find the physical tile in the fast look-up */ + auto physical_tile_search_result = physical_tile_pin_subtile_indices_.find(physical_tile); + if (physical_tile_search_result == physical_tile_pin_subtile_indices_.end()) { + /* Not found. Return an invalid index */ + return -1; + } + + /* Try to find the physical tile port info with pin index */ + auto pin_search_result = physical_tile_search_result->second.find(pin_index); + if (pin_search_result == physical_tile_search_result->second.end()) { + /* Not found. Return an invalid index */ + return -1; + } + + /* Reach here, we should find a port. Return the port information */ + return pin_search_result->second; +} + /************************************************************************ * Public mutators ***********************************************************************/ @@ -533,4 +573,16 @@ void VprDeviceAnnotation::add_physical_lb_rr_graph(t_pb_graph_node* pb_graph_hea physical_lb_rr_graphs_[pb_graph_head] = lb_rr_graph; } +void VprDeviceAnnotation::add_physical_tile_pin2port_info_pair(t_physical_tile_type_ptr physical_tile, + const int& pin_index, + const BasicPort& port) { + physical_tile_pin2port_info_map_[physical_tile][pin_index] = port; +} + +void VprDeviceAnnotation::add_physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile, + const int& pin_index, + const int& subtile_index) { + physical_tile_pin_subtile_indices_[physical_tile][pin_index] = subtile_index; +} + } /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/vpr_device_annotation.h b/openfpga/src/annotation/vpr_device_annotation.h index 0e290f18e..b5afbda00 100644 --- a/openfpga/src/annotation/vpr_device_annotation.h +++ b/openfpga/src/annotation/vpr_device_annotation.h @@ -81,6 +81,10 @@ class VprDeviceAnnotation { CircuitModelId rr_segment_circuit_model(const RRSegmentId& rr_segment) const; ArchDirectId direct_annotation(const size_t& direct) const; LbRRGraph physical_lb_rr_graph(t_pb_graph_node* pb_graph_head) const; + BasicPort physical_tile_pin_port_info(t_physical_tile_type_ptr physical_tile, + const int& pin_index) const; + int physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile, + const int& pin_index) const; public: /* Public mutators */ void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode); void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type); @@ -110,6 +114,12 @@ class VprDeviceAnnotation { void add_rr_segment_circuit_model(const RRSegmentId& rr_segment, const CircuitModelId& circuit_model); void add_direct_annotation(const size_t& direct, const ArchDirectId& arch_direct_id); void add_physical_lb_rr_graph(t_pb_graph_node* pb_graph_head, const LbRRGraph& lb_rr_graph); + void add_physical_tile_pin2port_info_pair(t_physical_tile_type_ptr physical_tile, + const int& pin_index, + const BasicPort& port); + void add_physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile, + const int& pin_index, + const int& subtile_index); private: /* Internal data */ /* Pair a regular pb_type to its physical pb_type */ std::map physical_pb_types_; @@ -197,6 +207,11 @@ class VprDeviceAnnotation { /* Logical type routing resource graphs built from physical modes */ std::map physical_lb_rr_graphs_; + + /* A fast look-up from pin index in physical tile to physical tile port */ + std::map> physical_tile_pin2port_info_map_; + /* A fast look-up from pin index in physical tile to sub tile index */ + std::map> physical_tile_pin_subtile_indices_; }; } /* End namespace openfpga*/ diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp index f33a292c6..63a0b0430 100644 --- a/openfpga/src/base/openfpga_link_arch.cpp +++ b/openfpga/src/base/openfpga_link_arch.cpp @@ -16,6 +16,7 @@ #include "vpr_device_annotation.h" #include "pb_type_utils.h" +#include "annotate_physical_tiles.h" #include "annotate_pb_types.h" #include "annotate_pb_graph.h" #include "annotate_routing.h" @@ -72,6 +73,10 @@ int link_arch(OpenfpgaContext& openfpga_ctx, CommandOptionId opt_sort_edge = cmd.option("sort_gsb_chan_node_in_edges"); CommandOptionId opt_verbose = cmd.option("verbose"); + /* Build fast look-up between physical tile pin index and port information */ + build_physical_tile_pin2port_info(g_vpr_ctx.device(), + openfpga_ctx.mutable_vpr_device_annotation()); + /* Annotate pb_type graphs * - physical pb_type * - mode selection bits for pb_type and pb interconnect diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp index 192015ddf..a0cfa551f 100644 --- a/openfpga/src/base/openfpga_naming.cpp +++ b/openfpga/src/base/openfpga_naming.cpp @@ -508,9 +508,11 @@ std::string generate_connection_block_module_name(const t_rr_type& cb_type, std::string generate_grid_port_name(const vtr::Point& coordinate, const size_t& width, const size_t& height, + const int& subtile_index, const e_side& side, - const size_t& pin_id, + const BasicPort& pin_info, const bool& for_top_netlist) { + VTR_ASSERT(1 == pin_info.get_width()); if (true == for_top_netlist) { std::string port_name = std::string("grid_"); port_name += std::to_string(coordinate.x()); @@ -521,7 +523,9 @@ std::string generate_grid_port_name(const vtr::Point& coordinate, port_name += std::string("__"); port_name += std::to_string(size_t(side)); port_name += std::string("__"); - port_name += std::to_string(pin_id); + port_name += pin_info.get_name(); + port_name += std::string("_"); + port_name += std::to_string(pin_info.get_lsb()); port_name += std::string("_"); return port_name; } @@ -533,8 +537,12 @@ std::string generate_grid_port_name(const vtr::Point& coordinate, port_name += std::to_string(width); port_name += std::string("_height_"); port_name += std::to_string(height); + port_name += std::string("_subtile_"); + port_name += std::to_string(subtile_index); port_name += std::string("__pin_"); - port_name += std::to_string(pin_id); + port_name += pin_info.get_name(); + port_name += std::string("_"); + port_name += std::to_string(pin_info.get_lsb()); port_name += std::string("_"); return port_name; } @@ -547,9 +555,11 @@ std::string generate_grid_port_name(const vtr::Point& coordinate, *********************************************************************/ std::string generate_grid_duplicated_port_name(const size_t& width, const size_t& height, + const int& subtile_index, const e_side& side, - const size_t& pin_id, + const BasicPort& pin_info, const bool& upper_port) { + VTR_ASSERT(1 == pin_info.get_width()); /* For non-top netlist */ SideManager side_manager(side); std::string port_name = std::string(side_manager.to_string()); @@ -557,8 +567,12 @@ std::string generate_grid_duplicated_port_name(const size_t& width, port_name += std::to_string(width); port_name += std::string("_height_"); port_name += std::to_string(height); + port_name += std::string("_subtile_"); + port_name += std::to_string(subtile_index); port_name += std::string("__pin_"); - port_name += std::to_string(pin_id); + port_name += pin_info.get_name(); + port_name += std::string("_"); + port_name += std::to_string(pin_info.get_lsb()); port_name += std::string("_"); if (true == upper_port) { @@ -586,27 +600,6 @@ std::string generate_grid_module_port_name(const size_t& pin_id) { return port_name; } -/********************************************************************* - * Generate the port name for a Grid - * This is a wrapper function for generate_port_name() - * which can automatically decode the port name by the pin side and height - *********************************************************************/ -std::string generate_grid_side_port_name(const DeviceGrid& grids, - const vtr::Point& coordinate, - const e_side& side, - const size_t& pin_id) { - /* Output the pins on the side*/ - size_t width = grids[coordinate.x()][coordinate.y()].type->pin_width_offset[pin_id]; - size_t height = grids[coordinate.x()][coordinate.y()].type->pin_height_offset[pin_id]; - if (true != grids[coordinate.x()][coordinate.y()].type->pinloc[width][height][side][pin_id]) { - SideManager side_manager(side); - VTR_LOG_ERROR("Fail to generate a grid pin (x=%lu, y=%lu, width=%lu, height=%lu, side=%s, index=%d)\n", - coordinate.x(), coordinate.y(), width, height, side_manager.c_str(), pin_id); - exit(1); - } - return generate_grid_port_name(coordinate, width, height, side, pin_id, true); -} - /********************************************************************* * Generate the port name of a grid pin for a routing module, * which could be a switch block or a connection block diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h index a3cfac08c..2b384b205 100644 --- a/openfpga/src/base/openfpga_naming.h +++ b/openfpga/src/base/openfpga_naming.h @@ -15,6 +15,7 @@ #include "vtr_geometry.h" #include "circuit_library.h" #include "device_grid.h" +#include "openfpga_port.h" /******************************************************************** * Function declaration @@ -137,23 +138,20 @@ std::string generate_pb_memory_instance_name(const std::string& prefix, std::string generate_grid_port_name(const vtr::Point& coordinate, const size_t& width, const size_t& height, + const int& subtile_index, const e_side& side, - const size_t& pin_id, + const BasicPort& pin_info, const bool& for_top_netlist); std::string generate_grid_duplicated_port_name(const size_t& width, const size_t& height, + const int& subtile_index, const e_side& side, - const size_t& pin_id, + const BasicPort& pin_info, const bool& upper_port); std::string generate_grid_module_port_name(const size_t& pin_id); -std::string generate_grid_side_port_name(const DeviceGrid& grids, - const vtr::Point& coordinate, - const e_side& side, - const size_t& pin_id); - std::string generate_sb_module_grid_port_name(const e_side& sb_side, const e_side& grid_side, const size_t& pin_id); diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 0df7c4aa7..4b39a5cee 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -113,6 +113,7 @@ int build_device_module_graph(ModuleManager& module_manager, status = build_top_module(module_manager, decoder_lib, openfpga_ctx.arch().circuit_lib, + openfpga_ctx.vpr_device_annotation(), vpr_device_ctx.grid, openfpga_ctx.arch().tile_annotations, vpr_device_ctx.rr_graph, diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp index 3efc7b011..4f354cd98 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp @@ -55,6 +55,7 @@ namespace openfpga { *******************************************************************/ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, const ModuleId& grid_module, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) { /* Ensure that we have a valid grid_type_descriptor */ @@ -87,6 +88,11 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, /* Reach here, it means this pin is on this side */ int class_id = grid_type_descriptor->pin_class[ipin]; e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type; + + BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, ipin); + VTR_ASSERT(true == pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, ipin); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); /* Generate the pin name * For each RECEIVER PIN or DRIVER PIN for direct connection, * we do not duplicate in these cases */ @@ -95,7 +101,7 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, || ( (DRIVER == pin_class_type) && (0. == find_physical_tile_pin_Fc(grid_type_descriptor, ipin)) ) ) { vtr::Point dummy_coordinate; - std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, side, ipin, false); + std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, subtile_index, side, pin_info, false); BasicPort grid_port(port_name, 0, 0); /* Add the port to the module */ module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]); @@ -105,12 +111,12 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, * The other with a postfix of lower, indicating it is located on the lower part of a side */ VTR_ASSERT(DRIVER == pin_class_type); - std::string upper_port_name = generate_grid_duplicated_port_name(iwidth, iheight, side, ipin, true); + std::string upper_port_name = generate_grid_duplicated_port_name(iwidth, iheight, subtile_index, side, pin_info, true); BasicPort grid_upper_port(upper_port_name, 0, 0); /* Add the port to the module */ module_manager.add_port(grid_module, grid_upper_port, pin_type2type_map[pin_class_type]); - std::string lower_port_name = generate_grid_duplicated_port_name(iwidth, iheight, side, ipin, false); + std::string lower_port_name = generate_grid_duplicated_port_name(iwidth, iheight, subtile_index, side, pin_info, false); BasicPort grid_lower_port(lower_port_name, 0, 0); /* Add the port to the module */ module_manager.add_port(grid_module, grid_lower_port, pin_type2type_map[pin_class_type]); @@ -134,6 +140,7 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin, const e_side& border_side, @@ -162,6 +169,12 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m int pin_width = grid_type_descriptor->pin_width_offset[grid_pin_index]; int pin_height = grid_type_descriptor->pin_height_offset[grid_pin_index]; + + BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, grid_pin_index); + VTR_ASSERT(true == pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); + for (const e_side& side : grid_pin_sides) { if (true != grid_type_descriptor->pinloc[pin_width][pin_height][side][grid_pin_index]) { continue; @@ -176,7 +189,7 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m ModuleNetId net = module_manager.create_module_net(grid_module); /* Find the port in grid_module */ vtr::Point dummy_coordinate; - std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, side, grid_pin_index, false); + std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, subtile_index, side, pin_info, false); ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id)); @@ -200,12 +213,12 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m /* Create a net to connect the grid pin to child module pin */ ModuleNetId net = module_manager.create_module_net(grid_module); /* Find the upper port in grid_module */ - std::string grid_upper_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, side, grid_pin_index, true); + std::string grid_upper_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, subtile_index, side, pin_info, true); ModulePortId grid_module_upper_port_id = module_manager.find_module_port(grid_module, grid_upper_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_upper_port_id)); /* Find the lower port in grid_module */ - std::string grid_lower_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, side, grid_pin_index, false); + std::string grid_lower_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, subtile_index, side, pin_info, false); ModulePortId grid_module_lower_port_id = module_manager.find_module_port(grid_module, grid_lower_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_lower_port_id)); @@ -238,6 +251,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) { /* Ensure that we have a valid grid_type_descriptor */ @@ -251,6 +265,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) { add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, child_module, child_instance, + vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->input_pins[iport][ipin]), border_side, @@ -263,6 +278,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) { add_grid_module_net_connect_duplicated_pb_graph_pin(module_manager, grid_module, child_module, child_instance, + vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->output_pins[iport][ipin]), border_side, @@ -274,6 +290,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) { add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, child_module, child_instance, + vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->clock_pins[iport][ipin]), border_side, diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.h b/openfpga/src/fabric/build_grid_module_duplicated_pins.h index 2bdd56dea..f60aaf1c7 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.h +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.h @@ -6,6 +6,7 @@ *******************************************************************/ #include "physical_types.h" #include "module_manager.h" +#include "vpr_device_annotation.h" #include "openfpga_side_manager.h" /******************************************************************** @@ -17,6 +18,7 @@ namespace openfpga { void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, const ModuleId& grid_module, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side); @@ -24,6 +26,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side); diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp index 60e44a435..8afe1ed1c 100644 --- a/openfpga/src/fabric/build_grid_module_utils.cpp +++ b/openfpga/src/fabric/build_grid_module_utils.cpp @@ -46,6 +46,7 @@ void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager, const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin, const e_side& border_side, @@ -79,7 +80,11 @@ void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager, ModuleNetId net = module_manager.create_module_net(grid_module); /* Find the port in grid_module */ vtr::Point dummy_coordinate; - std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, side, grid_pin_index, false); + BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, grid_pin_index); + VTR_ASSERT(true == pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); + std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, subtile_index, side, pin_info, false); ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id)); /* Grid port always has only 1 pin, it is assumed when adding these ports to the module diff --git a/openfpga/src/fabric/build_grid_module_utils.h b/openfpga/src/fabric/build_grid_module_utils.h index cf7b2d2d6..5a2a17490 100644 --- a/openfpga/src/fabric/build_grid_module_utils.h +++ b/openfpga/src/fabric/build_grid_module_utils.h @@ -9,6 +9,7 @@ #include "openfpga_interconnect_types.h" #include "module_manager.h" +#include "vpr_device_annotation.h" /******************************************************************** * Function declaration @@ -24,6 +25,7 @@ void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager, const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin, const e_side& border_side, diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index f9af7d722..8447d8edb 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -41,6 +41,7 @@ namespace openfpga { static void add_grid_module_pb_type_ports(ModuleManager& module_manager, const ModuleId& grid_module, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) { /* Ensure that we have a valid grid_type_descriptor */ @@ -77,7 +78,11 @@ void add_grid_module_pb_type_ports(ModuleManager& module_manager, * we give a empty coordinate but it will not be used (see details in the function */ vtr::Point dummy_coordinate; - std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, side, ipin, false); + BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, ipin); + VTR_ASSERT(true == pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, ipin); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); + std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, subtile_index, side, pin_info, false); BasicPort grid_port(port_name, 0, 0); /* Add the port to the module */ module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]); @@ -99,6 +104,7 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) { /* Ensure that we have a valid grid_type_descriptor */ @@ -112,6 +118,7 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) { add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, child_module, child_instance, + vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->input_pins[iport][ipin]), border_side, @@ -124,6 +131,7 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) { add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, child_module, child_instance, + vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->output_pins[iport][ipin]), border_side, @@ -135,6 +143,7 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) { add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, child_module, child_instance, + vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->clock_pins[iport][ipin]), border_side, @@ -974,6 +983,7 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager, static void build_physical_tile_module(ModuleManager& module_manager, DecoderLibrary& decoder_lib, + const VprDeviceAnnotation& vpr_device_annotation, const CircuitLibrary& circuit_lib, const e_config_protocol_type& sram_orgz_type, const CircuitModelId& sram_model, @@ -1035,6 +1045,7 @@ void build_physical_tile_module(ModuleManager& module_manager, if (false == duplicate_grid_pin) { /* Default way to add these ports by following the definition in pb_types */ add_grid_module_pb_type_ports(module_manager, grid_module, + vpr_device_annotation, phy_block_type, border_side); /* Add module nets to connect the pb_type ports to sub modules */ for (t_logical_block_type_ptr lb_type : phy_block_type->equivalent_sites) { @@ -1048,6 +1059,7 @@ void build_physical_tile_module(ModuleManager& module_manager, for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_pb_type_ports(module_manager, grid_module, pb_module, child_instance, + vpr_device_annotation, phy_block_type, border_side); } } @@ -1055,6 +1067,7 @@ void build_physical_tile_module(ModuleManager& module_manager, VTR_ASSERT_SAFE(true == duplicate_grid_pin); /* Add these ports with duplication */ add_grid_module_duplicated_pb_type_ports(module_manager, grid_module, + vpr_device_annotation, phy_block_type, border_side); /* Add module nets to connect the duplicated pb_type ports to sub modules */ @@ -1069,6 +1082,7 @@ void build_physical_tile_module(ModuleManager& module_manager, for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_duplicated_pb_type_ports(module_manager, grid_module, pb_module, child_instance, + vpr_device_annotation, phy_block_type, border_side); } } @@ -1186,6 +1200,7 @@ void build_grid_modules(ModuleManager& module_manager, &physical_tile); for (const e_side& io_type_side : io_type_sides) { build_physical_tile_module(module_manager, decoder_lib, + device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, @@ -1196,6 +1211,7 @@ void build_grid_modules(ModuleManager& module_manager, } else { /* For CLB and heterogenenous blocks */ build_physical_tile_module(module_manager, decoder_lib, + device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 9e1bd7857..56b7d4b2b 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -284,6 +284,7 @@ vtr::Matrix add_top_module_connection_block_instances(ModuleManager& mod int build_top_module(ModuleManager& module_manager, DecoderLibrary& decoder_lib, const CircuitLibrary& circuit_lib, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const TileAnnotation& tile_annotation, const RRGraph& rr_graph, @@ -329,11 +330,13 @@ int build_top_module(ModuleManager& module_manager, /* Add module nets to connect the sub modules */ add_top_module_nets_connect_grids_and_gsbs(module_manager, top_module, + vpr_device_annotation, grids, grid_instance_ids, rr_graph, device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy, duplicate_grid_pin); /* Add inter-CLB direct connections */ add_top_module_nets_tile_direct_connections(module_manager, top_module, circuit_lib, + vpr_device_annotation, grids, grid_instance_ids, tile_direct, arch_direct); } @@ -345,7 +348,7 @@ int build_top_module(ModuleManager& module_manager, add_module_global_ports_from_child_modules(module_manager, top_module); /* Add global ports from grid ports that are defined as global in tile annotation */ - status = add_top_module_global_ports_from_grid_modules(module_manager, top_module, tile_annotation, grids, grid_instance_ids); + status = add_top_module_global_ports_from_grid_modules(module_manager, top_module, tile_annotation, vpr_device_annotation, grids, grid_instance_ids); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h index 1905a3b1b..d7e90a09f 100644 --- a/openfpga/src/fabric/build_top_module.h +++ b/openfpga/src/fabric/build_top_module.h @@ -8,6 +8,7 @@ #include #include "vtr_geometry.h" #include "device_grid.h" +#include "vpr_device_annotation.h" #include "tile_annotation.h" #include "rr_graph_obj.h" #include "device_rr_gsb.h" @@ -29,6 +30,7 @@ namespace openfpga { int build_top_module(ModuleManager& module_manager, DecoderLibrary& decoder_lib, const CircuitLibrary& circuit_lib, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const TileAnnotation& tile_annotation, const RRGraph& rr_graph, diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 870d21340..559f50978 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -64,6 +64,7 @@ namespace openfpga { static void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const RRGraph& rr_graph, @@ -112,11 +113,17 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; size_t src_grid_pin_index = rr_graph.node_pin_num(rr_gsb.get_opin_node(side_manager.get_side(), inode)); - size_t src_grid_pin_width = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_width_offset[src_grid_pin_index]; - size_t src_grid_pin_height = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_height_offset[src_grid_pin_index]; - std::string src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height, + + t_physical_tile_type_ptr grid_type_descriptor = grids[grid_coordinate.x()][grid_coordinate.y()].type; + size_t src_grid_pin_width = grid_type_descriptor->pin_width_offset[src_grid_pin_index]; + size_t src_grid_pin_height = grid_type_descriptor->pin_height_offset[src_grid_pin_index]; + BasicPort src_grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, src_grid_pin_index); + VTR_ASSERT(true == src_grid_pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, src_grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); + std::string src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height, subtile_index, rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)), - src_grid_pin_index, false); + src_grid_pin_info, false); ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id)); BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id); @@ -184,6 +191,7 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, static void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const RRGraph& rr_graph, @@ -242,8 +250,15 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; size_t src_grid_pin_index = rr_graph.node_pin_num(rr_gsb.get_opin_node(side_manager.get_side(), inode)); - size_t src_grid_pin_width = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_width_offset[src_grid_pin_index]; - size_t src_grid_pin_height = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_height_offset[src_grid_pin_index]; + + t_physical_tile_type_ptr grid_type_descriptor = grids[grid_coordinate.x()][grid_coordinate.y()].type; + size_t src_grid_pin_width = grid_type_descriptor->pin_width_offset[src_grid_pin_index]; + size_t src_grid_pin_height = grid_type_descriptor->pin_height_offset[src_grid_pin_index]; + + BasicPort src_grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, src_grid_pin_index); + VTR_ASSERT(true == src_grid_pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, src_grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); /* Pins for direct connection are NOT duplicated. * Follow the traditional recipe when adding nets! @@ -251,14 +266,14 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager * For other duplicated pins, we follow the new naming */ std::string src_grid_port_name; - if (0. == find_physical_tile_pin_Fc(grids[grid_coordinate.x()][grid_coordinate.y()].type, src_grid_pin_index)) { - src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height, + if (0. == find_physical_tile_pin_Fc(grid_type_descriptor, src_grid_pin_index)) { + src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height, subtile_index, rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)), - src_grid_pin_index, false); + src_grid_pin_info, false); } else { - src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_width, src_grid_pin_height, + src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_width, src_grid_pin_height, subtile_index, rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)), - src_grid_pin_index, sb_side2postfix_map[side_manager.get_side()]); + src_grid_pin_info, sb_side2postfix_map[side_manager.get_side()]); } ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id)); @@ -346,6 +361,7 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager static void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const RRGraph& rr_graph, @@ -414,11 +430,17 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); size_t sink_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_ipin_node); - size_t sink_grid_pin_width = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_width_offset[sink_grid_pin_index]; - size_t sink_grid_pin_height = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_height_offset[sink_grid_pin_index]; - std::string sink_grid_port_name = generate_grid_port_name(grid_coordinate, sink_grid_pin_width, sink_grid_pin_height, + + t_physical_tile_type_ptr grid_type_descriptor = grids[grid_coordinate.x()][grid_coordinate.y()].type; + size_t sink_grid_pin_width = grid_type_descriptor->pin_width_offset[sink_grid_pin_index]; + size_t sink_grid_pin_height = grid_type_descriptor->pin_height_offset[sink_grid_pin_index]; + BasicPort sink_grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, sink_grid_pin_index); + VTR_ASSERT(true == sink_grid_pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, sink_grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); + std::string sink_grid_port_name = generate_grid_port_name(grid_coordinate, sink_grid_pin_width, sink_grid_pin_height, subtile_index, rr_graph.node_side(rr_gsb.get_ipin_node(cb_ipin_side, inode)), - sink_grid_pin_index, false); + sink_grid_pin_info, false); ModulePortId sink_grid_port_id = module_manager.find_module_port(sink_grid_module, sink_grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_grid_port_id)); BasicPort sink_grid_port = module_manager.module_port(sink_grid_module, sink_grid_port_id); @@ -640,6 +662,7 @@ void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, *******************************************************************/ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const RRGraph& rr_graph, @@ -661,23 +684,27 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, /* Connect the grid pins of the GSB to adjacent grids */ if (false == duplicate_grid_pin) { add_top_module_nets_connect_grids_and_sb(module_manager, top_module, + vpr_device_annotation, grids, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, compact_routing_hierarchy); } else { VTR_ASSERT_SAFE(true == duplicate_grid_pin); add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(module_manager, top_module, + vpr_device_annotation, grids, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, compact_routing_hierarchy); } add_top_module_nets_connect_grids_and_cb(module_manager, top_module, + vpr_device_annotation, grids, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANX, cb_instance_ids.at(CHANX), compact_routing_hierarchy); add_top_module_nets_connect_grids_and_cb(module_manager, top_module, + vpr_device_annotation, grids, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANY, cb_instance_ids.at(CHANY), compact_routing_hierarchy); @@ -701,6 +728,7 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana const TileAnnotation& tile_annotation, const TileGlobalPortId& tile_global_port, const BasicPort& tile_port_to_connect, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Point& grid_coordinate, const e_side& border_side, @@ -757,12 +785,17 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana size_t grid_pin_height = physical_tile->pin_height_offset[grid_pin_index]; std::vector pin_sides = find_physical_tile_pin_side(physical_tile, grid_pin_index, border_side); + BasicPort grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, grid_pin_index); + VTR_ASSERT(true == grid_pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(physical_tile, grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && subtile_index < physical_tile->capacity); + /* Build nets */ for (const e_side& pin_side : pin_sides) { std::string grid_port_name = generate_grid_port_name(grid_coordinate, - grid_pin_width, grid_pin_height, + grid_pin_width, grid_pin_height, subtile_index, pin_side, - grid_pin_index, false); + grid_pin_info, false); ModulePortId grid_port_id = module_manager.find_module_port(grid_module, grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_port_id)); @@ -789,6 +822,7 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager, const ModuleId& top_module, const TileAnnotation& tile_annotation, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids) { int status = CMD_EXEC_SUCCESS; @@ -888,6 +922,7 @@ int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager, tile_annotation, tile_global_port, tile_port, + vpr_device_annotation, grids, vtr::Point(ix, iy), NUM_SIDES, @@ -935,6 +970,7 @@ int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager, tile_annotation, tile_global_port, tile_port, + vpr_device_annotation, grids, io_coordinate, io_side, diff --git a/openfpga/src/fabric/build_top_module_connection.h b/openfpga/src/fabric/build_top_module_connection.h index d400205d2..dd44455a6 100644 --- a/openfpga/src/fabric/build_top_module_connection.h +++ b/openfpga/src/fabric/build_top_module_connection.h @@ -11,6 +11,7 @@ #include "rr_graph_obj.h" #include "device_rr_gsb.h" #include "tile_annotation.h" +#include "vpr_device_annotation.h" #include "module_manager.h" /******************************************************************** @@ -22,6 +23,7 @@ namespace openfpga { void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const RRGraph& rr_graph, @@ -34,6 +36,7 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager, const ModuleId& top_module, const TileAnnotation& tile_annotation, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids); diff --git a/openfpga/src/fabric/build_top_module_directs.cpp b/openfpga/src/fabric/build_top_module_directs.cpp index 5f53fdd5b..fbcffaf4a 100644 --- a/openfpga/src/fabric/build_top_module_directs.cpp +++ b/openfpga/src/fabric/build_top_module_directs.cpp @@ -41,6 +41,7 @@ static void add_module_nets_tile_direct_connection(ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const TileDirect& tile_direct, @@ -92,9 +93,16 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager, /* Generate the pin name of source port/pin in the grid */ e_side src_pin_grid_side = tile_direct.from_tile_side(tile_direct_id); size_t src_tile_pin = tile_direct.from_tile_pin(tile_direct_id); - size_t src_pin_width = grids[src_clb_coord.x()][src_clb_coord.y()].type->pin_width_offset[src_tile_pin]; - size_t src_pin_height = grids[src_clb_coord.x()][src_clb_coord.y()].type->pin_height_offset[src_tile_pin]; - std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_width, src_pin_height, src_pin_grid_side, src_tile_pin, false); + + t_physical_tile_type_ptr src_grid_type_descriptor = grids[src_clb_coord.x()][src_clb_coord.y()].type; + size_t src_pin_width = src_grid_type_descriptor->pin_width_offset[src_tile_pin]; + size_t src_pin_height = src_grid_type_descriptor->pin_height_offset[src_tile_pin]; + + BasicPort src_pin_info = vpr_device_annotation.physical_tile_pin_port_info(src_grid_type_descriptor, src_tile_pin); + VTR_ASSERT(true == src_pin_info.is_valid()); + int src_subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(src_grid_type_descriptor, src_tile_pin); + VTR_ASSERT(OPEN != src_subtile_index && src_subtile_index < src_grid_type_descriptor->capacity); + std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_width, src_pin_height, src_subtile_index, src_pin_grid_side, src_pin_info, false); ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name); if (true != module_manager.valid_module_port_id(src_grid_module, src_port_id)) { VTR_LOG_ERROR("Fail to find port '%s[%lu][%lu].%s'\n", @@ -107,10 +115,16 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager, /* Generate the pin name of sink port/pin in the grid */ e_side sink_pin_grid_side = tile_direct.to_tile_side(tile_direct_id); size_t sink_tile_pin = tile_direct.to_tile_pin(tile_direct_id); - size_t sink_pin_width = grids[des_clb_coord.x()][des_clb_coord.y()].type->pin_width_offset[src_tile_pin]; - size_t sink_pin_height = grids[des_clb_coord.x()][des_clb_coord.y()].type->pin_height_offset[src_tile_pin]; - std::string sink_port_name = generate_grid_port_name(des_clb_coord, sink_pin_width, sink_pin_height, sink_pin_grid_side, sink_tile_pin, false); + t_physical_tile_type_ptr sink_grid_type_descriptor = grids[des_clb_coord.x()][des_clb_coord.y()].type; + size_t sink_pin_width = sink_grid_type_descriptor->pin_width_offset[src_tile_pin]; + size_t sink_pin_height = sink_grid_type_descriptor->pin_height_offset[src_tile_pin]; + + BasicPort sink_pin_info = vpr_device_annotation.physical_tile_pin_port_info(sink_grid_type_descriptor, sink_tile_pin); + VTR_ASSERT(true == sink_pin_info.is_valid()); + int sink_subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(sink_grid_type_descriptor, sink_tile_pin); + VTR_ASSERT(OPEN != src_subtile_index && src_subtile_index < sink_grid_type_descriptor->capacity); + std::string sink_port_name = generate_grid_port_name(des_clb_coord, sink_pin_width, sink_pin_height, sink_subtile_index, sink_pin_grid_side, sink_pin_info, false); ModulePortId sink_port_id = module_manager.find_module_port(sink_grid_module, sink_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_port_id)); VTR_ASSERT(1 == module_manager.module_port(sink_grid_module, sink_port_id).get_width()); @@ -141,6 +155,7 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager, void add_top_module_nets_tile_direct_connections(ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const TileDirect& tile_direct, @@ -150,6 +165,7 @@ void add_top_module_nets_tile_direct_connections(ModuleManager& module_manager, for (const TileDirectId& tile_direct_id : tile_direct.directs()) { add_module_nets_tile_direct_connection(module_manager, top_module, circuit_lib, + vpr_device_annotation, grids, grid_instance_ids, tile_direct, tile_direct_id, arch_direct); diff --git a/openfpga/src/fabric/build_top_module_directs.h b/openfpga/src/fabric/build_top_module_directs.h index e9855db70..aa46f0ec8 100644 --- a/openfpga/src/fabric/build_top_module_directs.h +++ b/openfpga/src/fabric/build_top_module_directs.h @@ -9,6 +9,7 @@ #include "vtr_ndmatrix.h" #include "arch_direct.h" #include "tile_direct.h" +#include "vpr_device_annotation.h" #include "device_grid.h" #include "module_manager.h" #include "circuit_library.h" @@ -23,6 +24,7 @@ namespace openfpga { void add_top_module_nets_tile_direct_connections(ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const TileDirect& tile_direct,