From 185e574738ae91e7b56fb380b4bea910835fae07 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 24 Apr 2020 20:21:32 -0600 Subject: [PATCH 01/35] removed redundant include files in all the verilog netlists except the top one --- openfpga/src/fpga_verilog/verilog_api.cpp | 13 +++++------- .../src/fpga_verilog/verilog_decoders.cpp | 3 --- openfpga/src/fpga_verilog/verilog_decoders.h | 1 - .../fpga_verilog/verilog_essential_gates.cpp | 3 --- .../fpga_verilog/verilog_essential_gates.h | 1 - .../verilog_formal_random_top_testbench.cpp | 6 ------ .../verilog_formal_random_top_testbench.h | 1 - openfpga/src/fpga_verilog/verilog_grid.cpp | 15 +++----------- openfpga/src/fpga_verilog/verilog_grid.h | 1 - openfpga/src/fpga_verilog/verilog_lut.cpp | 3 --- openfpga/src/fpga_verilog/verilog_lut.h | 1 - openfpga/src/fpga_verilog/verilog_memory.cpp | 3 --- openfpga/src/fpga_verilog/verilog_memory.h | 1 - openfpga/src/fpga_verilog/verilog_mux.cpp | 3 --- openfpga/src/fpga_verilog/verilog_mux.h | 1 - .../verilog_preconfig_top_module.cpp | 8 +------- .../verilog_preconfig_top_module.h | 3 +-- openfpga/src/fpga_verilog/verilog_routing.cpp | 20 ++----------------- openfpga/src/fpga_verilog/verilog_routing.h | 2 -- .../src/fpga_verilog/verilog_submodule.cpp | 14 ++++++------- openfpga/src/fpga_verilog/verilog_submodule.h | 1 - .../fpga_verilog/verilog_submodule_utils.cpp | 3 --- .../fpga_verilog/verilog_submodule_utils.h | 1 - .../src/fpga_verilog/verilog_top_module.cpp | 3 --- .../fpga_verilog/verilog_top_testbench.cpp | 4 ---- .../src/fpga_verilog/verilog_top_testbench.h | 1 - openfpga/src/fpga_verilog/verilog_wire.cpp | 3 --- openfpga/src/fpga_verilog/verilog_wire.h | 1 - 28 files changed, 18 insertions(+), 102 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp index d2823df48..c8c7343ad 100644 --- a/openfpga/src/fpga_verilog/verilog_api.cpp +++ b/openfpga/src/fpga_verilog/verilog_api.cpp @@ -91,7 +91,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager, */ print_verilog_submodule(module_manager, netlist_manager, mux_lib, circuit_lib, - src_dir_path, submodule_dir_path, + submodule_dir_path, options); /* Generate routing blocks */ @@ -99,14 +99,14 @@ void fpga_fabric_verilog(ModuleManager& module_manager, print_verilog_unique_routing_modules(netlist_manager, const_cast(module_manager), device_rr_gsb, - src_dir_path, rr_dir_path, + rr_dir_path, options.explicit_port_mapping()); } else { VTR_ASSERT(false == options.compress_routing()); print_verilog_flatten_routing_modules(netlist_manager, const_cast(module_manager), device_rr_gsb, - src_dir_path, rr_dir_path, + rr_dir_path, options.explicit_port_mapping()); } @@ -114,7 +114,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager, print_verilog_grids(netlist_manager, const_cast(module_manager), device_ctx, device_annotation, - src_dir_path, lb_dir_path, + lb_dir_path, options.explicit_port_mapping(), options.verbose_output()); @@ -180,8 +180,7 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager, atom_ctx, place_ctx, io_location_map, netlist_annotation, netlist_name, - formal_verification_top_netlist_file_path, - src_dir_path); + formal_verification_top_netlist_file_path); } if (true == options.print_preconfig_top_testbench()) { @@ -190,7 +189,6 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager, + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX); print_verilog_random_top_testbench(netlist_name, random_top_testbench_file_path, - src_dir_path, atom_ctx, netlist_annotation, simulation_setting); @@ -208,7 +206,6 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager, netlist_annotation, netlist_name, top_testbench_file_path, - src_dir_path, simulation_setting); } diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp index 0e993a3d3..30789e36f 100644 --- a/openfpga/src/fpga_verilog/verilog_decoders.cpp +++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp @@ -165,7 +165,6 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir) { std::string verilog_fname(submodule_dir + std::string(LOCAL_ENCODER_VERILOG_FILE_NAME)); @@ -181,8 +180,6 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana print_verilog_file_header(fp, "Local Decoders for Multiplexers"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Create a library for local encoders with different sizes */ DecoderLibrary decoder_lib; diff --git a/openfpga/src/fpga_verilog/verilog_decoders.h b/openfpga/src/fpga_verilog/verilog_decoders.h index f8d559f4d..9b2bbb6b1 100644 --- a/openfpga/src/fpga_verilog/verilog_decoders.h +++ b/openfpga/src/fpga_verilog/verilog_decoders.h @@ -25,7 +25,6 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp index 20be3e7e4..cb8eb9504 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp @@ -527,7 +527,6 @@ void print_verilog_constant_generator_module(const ModuleManager& module_manager ***********************************************/ void print_verilog_submodule_essentials(const ModuleManager& module_manager, NetlistManager& netlist_manager, - const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib) { /* TODO: remove .bak when this part is completed and tested */ @@ -546,8 +545,6 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager, print_verilog_file_header(fp, "Essential gates"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Print constant generators */ /* VDD */ print_verilog_constant_generator_module(module_manager, fp, 0); diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.h b/openfpga/src/fpga_verilog/verilog_essential_gates.h index b267d0e6e..2510e6d3d 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.h +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.h @@ -18,7 +18,6 @@ namespace openfpga { void print_verilog_submodule_essentials(const ModuleManager& module_manager, NetlistManager& netlist_manager, - const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib); diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index fa4f68938..8d4dab5c9 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -183,7 +183,6 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, ********************************************************************/ void print_verilog_random_top_testbench(const std::string& circuit_name, const std::string& verilog_fname, - const std::string& verilog_dir, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, const SimulationSetting& simulation_parameters) { @@ -203,11 +202,6 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, std::string title = std::string("FPGA Verilog Testbench for Formal Top-level netlist of Design: ") + circuit_name; print_verilog_file_header(fp, title); - /* Print preprocessing flags and external netlists */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME))); - /* Preparation: find all the clock ports */ std::vector clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h index 88692ae4f..b12072b70 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h @@ -17,7 +17,6 @@ namespace openfpga { void print_verilog_random_top_testbench(const std::string& circuit_name, const std::string& verilog_fname, - const std::string& verilog_dir, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, const SimulationSetting& simulation_parameters); diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp index 0cf509bde..d2917836b 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.cpp +++ b/openfpga/src/fpga_verilog/verilog_grid.cpp @@ -197,7 +197,6 @@ static void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager, const ModuleManager& module_manager, const VprDeviceAnnotation& device_annotation, - const std::string& verilog_dir, const std::string& subckt_dir, t_pb_graph_node* pb_graph_head, const bool& use_explicit_mapping, @@ -220,9 +219,6 @@ void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager, print_verilog_file_header(fp, std::string("Verilog modules for logical tile: " + std::string(pb_graph_head->pb_type->name) + "]")); - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Print Verilog modules for all the pb_types/pb_graph_nodes * use a Depth-First Search Algorithm to print the sub-modules * Note: DFS is the right way. Do NOT use BFS. @@ -262,7 +258,6 @@ void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager, static void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager, const ModuleManager& module_manager, - const std::string& verilog_dir, const std::string& subckt_dir, t_physical_tile_type_ptr phy_block_type, const e_side& border_side, @@ -300,9 +295,6 @@ void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager, print_verilog_file_header(fp, std::string("Verilog modules for physical tile: " + std::string(phy_block_type->name) + "]")); - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Create a Verilog Module for the top-level physical block, and add to module manager */ std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_VERILOG_FILE_NAME_PREFIX), std::string(phy_block_type->name), is_io_type(phy_block_type), border_side); ModuleId grid_module = module_manager.find_module(grid_module_name); @@ -338,7 +330,6 @@ void print_verilog_grids(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation, - const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_mapping, const bool& verbose) { @@ -362,7 +353,7 @@ void print_verilog_grids(NetlistManager& netlist_manager, print_verilog_logical_tile_netlist(netlist_manager, module_manager, device_annotation, - verilog_dir, subckt_dir, + subckt_dir, logical_tile.pb_graph_head, use_explicit_mapping, verbose); @@ -395,7 +386,7 @@ void print_verilog_grids(NetlistManager& netlist_manager, for (const e_side& io_type_side : io_type_sides) { print_verilog_physical_tile_netlist(netlist_manager, module_manager, - verilog_dir, subckt_dir, + subckt_dir, &physical_tile, io_type_side, use_explicit_mapping); @@ -405,7 +396,7 @@ void print_verilog_grids(NetlistManager& netlist_manager, /* For CLB and heterogenenous blocks */ print_verilog_physical_tile_netlist(netlist_manager, module_manager, - verilog_dir, subckt_dir, + subckt_dir, &physical_tile, NUM_SIDES, use_explicit_mapping); diff --git a/openfpga/src/fpga_verilog/verilog_grid.h b/openfpga/src/fpga_verilog/verilog_grid.h index 6d2843628..7603bd298 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.h +++ b/openfpga/src/fpga_verilog/verilog_grid.h @@ -21,7 +21,6 @@ void print_verilog_grids(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation, - const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_mapping, const bool& verbose); diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp index fabe9340e..34767aff7 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.cpp +++ b/openfpga/src/fpga_verilog/verilog_lut.cpp @@ -32,7 +32,6 @@ namespace openfpga { void print_verilog_submodule_luts(const ModuleManager& module_manager, NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const bool& use_explicit_port_map) { std::string verilog_fname = submodule_dir + std::string(LUTS_VERILOG_FILE_NAME); @@ -50,8 +49,6 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager, print_verilog_file_header(fp, "Look-Up Tables"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Search for each LUT circuit model */ for (const auto& lut_model : circuit_lib.models()) { /* Bypass user-defined and non-LUT modules */ diff --git a/openfpga/src/fpga_verilog/verilog_lut.h b/openfpga/src/fpga_verilog/verilog_lut.h index e9ba3465a..a102e6df0 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.h +++ b/openfpga/src/fpga_verilog/verilog_lut.h @@ -21,7 +21,6 @@ namespace openfpga { void print_verilog_submodule_luts(const ModuleManager& module_manager, NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const bool& use_explicit_port_map); diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp index 53420a794..ad30eb337 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.cpp +++ b/openfpga/src/fpga_verilog/verilog_memory.cpp @@ -100,7 +100,6 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager, NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const bool& use_explicit_port_map) { /* Plug in with the mux subckt */ @@ -118,8 +117,6 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager, print_verilog_file_header(fp, "Memories used in FPGA"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Create the memory circuits for the multiplexer */ for (auto mux : mux_lib.muxes()) { const MuxGraph& mux_graph = mux_lib.mux_graph(mux); diff --git a/openfpga/src/fpga_verilog/verilog_memory.h b/openfpga/src/fpga_verilog/verilog_memory.h index a331e5687..f489df2ad 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.h +++ b/openfpga/src/fpga_verilog/verilog_memory.h @@ -23,7 +23,6 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager, NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const bool& use_explicit_port_map); diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp index c85978722..3b7d3300b 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.cpp +++ b/openfpga/src/fpga_verilog/verilog_mux.cpp @@ -1227,7 +1227,6 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const bool& use_explicit_port_map) { @@ -1245,8 +1244,6 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, print_verilog_file_header(fp, "Multiplexers"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Generate basis sub-circuit for unique branches shared by the multiplexers */ for (auto mux : mux_lib.muxes()) { const MuxGraph& mux_graph = mux_lib.mux_graph(mux); diff --git a/openfpga/src/fpga_verilog/verilog_mux.h b/openfpga/src/fpga_verilog/verilog_mux.h index c98fa77d0..361c394dc 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.h +++ b/openfpga/src/fpga_verilog/verilog_mux.h @@ -24,7 +24,6 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const bool& use_explicit_port_map); diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 695d9275f..8e1de5cfc 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -385,8 +385,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, const IoLocationMap& io_location_map, const VprNetlistAnnotation& netlist_annotation, const std::string& circuit_name, - const std::string& verilog_fname, - const std::string& verilog_dir) { + const std::string& verilog_fname) { std::string timer_message = std::string("Write pre-configured FPGA top-level Verilog netlist for design '") + circuit_name + std::string("'"); /* Start time count */ @@ -403,11 +402,6 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, std::string title = std::string("Verilog netlist for pre-configured FPGA fabric by design: ") + circuit_name; print_verilog_file_header(fp, title); - /* Print preprocessing flags and external netlists */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME))); - /* Print module declaration and ports */ print_verilog_preconfig_top_module_ports(fp, circuit_name, atom_ctx, netlist_annotation); diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h index 499cafea9..e8efe5f29 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h @@ -29,8 +29,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, const IoLocationMap& io_location_map, const VprNetlistAnnotation& netlist_annotation, const std::string& circuit_name, - const std::string& verilog_fname, - const std::string& verilog_dir); + const std::string& verilog_fname); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp index 8f74c0074..e6df8e858 100644 --- a/openfpga/src/fpga_verilog/verilog_routing.cpp +++ b/openfpga/src/fpga_verilog/verilog_routing.cpp @@ -77,7 +77,6 @@ namespace openfpga { static void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_manager, const ModuleManager& module_manager, - const std::string& verilog_dir, const std::string& subckt_dir, const RRGSB& rr_gsb, const t_rr_type& cb_type, @@ -94,9 +93,6 @@ void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_ print_verilog_file_header(fp, std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]")); - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Create a Verilog Module based on the circuit model, and add to module manager */ ModuleId cb_module = module_manager.find_module(generate_connection_block_module_name(cb_type, gsb_coordinate)); VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); @@ -182,7 +178,6 @@ void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_ static void print_verilog_routing_switch_box_unique_module(NetlistManager& netlist_manager, const ModuleManager& module_manager, - const std::string& verilog_dir, const std::string& subckt_dir, const RRGSB& rr_gsb, const bool& use_explicit_port_map) { @@ -198,9 +193,6 @@ void print_verilog_routing_switch_box_unique_module(NetlistManager& netlist_mana print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]")); - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Create a Verilog Module based on the circuit model, and add to module manager */ ModuleId sb_module = module_manager.find_module(generate_switch_block_module_name(gsb_coordinate)); VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); @@ -225,7 +217,6 @@ static void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, - const std::string& verilog_dir, const std::string& subckt_dir, const t_rr_type& cb_type, const bool& use_explicit_port_map) { @@ -244,7 +235,6 @@ void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_mana } print_verilog_routing_connection_box_unique_module(netlist_manager, module_manager, - verilog_dir, subckt_dir, rr_gsb, cb_type, use_explicit_port_map); @@ -264,7 +254,6 @@ void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_mana void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, - const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_port_map) { /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ @@ -281,16 +270,15 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager, } print_verilog_routing_switch_box_unique_module(netlist_manager, module_manager, - verilog_dir, subckt_dir, rr_gsb, use_explicit_port_map); } } - print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map); + print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, subckt_dir, CHANX, use_explicit_port_map); - print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map); + print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, subckt_dir, CHANY, use_explicit_port_map); /* VTR_LOG("Writing header file for routing submodules '%s'...", @@ -317,7 +305,6 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager, void print_verilog_unique_routing_modules(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, - const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_port_map) { /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ @@ -328,7 +315,6 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager, const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb); print_verilog_routing_switch_box_unique_module(netlist_manager, module_manager, - verilog_dir, subckt_dir, unique_mirror, use_explicit_port_map); @@ -340,7 +326,6 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager, print_verilog_routing_connection_box_unique_module(netlist_manager, module_manager, - verilog_dir, subckt_dir, unique_mirror, CHANX, use_explicit_port_map); @@ -352,7 +337,6 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager, print_verilog_routing_connection_box_unique_module(netlist_manager, module_manager, - verilog_dir, subckt_dir, unique_mirror, CHANY, use_explicit_port_map); diff --git a/openfpga/src/fpga_verilog/verilog_routing.h b/openfpga/src/fpga_verilog/verilog_routing.h index a9f8fd6a1..9d439053a 100644 --- a/openfpga/src/fpga_verilog/verilog_routing.h +++ b/openfpga/src/fpga_verilog/verilog_routing.h @@ -20,14 +20,12 @@ namespace openfpga { void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, - const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_port_map); void print_verilog_unique_routing_modules(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, - const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_port_map); diff --git a/openfpga/src/fpga_verilog/verilog_submodule.cpp b/openfpga/src/fpga_verilog/verilog_submodule.cpp index b38750ab9..37df77c60 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule.cpp +++ b/openfpga/src/fpga_verilog/verilog_submodule.cpp @@ -35,7 +35,6 @@ void print_verilog_submodule(ModuleManager& module_manager, NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const FabricVerilogOption& fpga_verilog_opts) { @@ -47,7 +46,6 @@ void print_verilog_submodule(ModuleManager& module_manager, print_verilog_submodule_essentials(const_cast(module_manager), netlist_manager, - verilog_dir, submodule_dir, circuit_lib); @@ -58,35 +56,35 @@ void print_verilog_submodule(ModuleManager& module_manager, print_verilog_submodule_mux_local_decoders(const_cast(module_manager), netlist_manager, mux_lib, circuit_lib, - verilog_dir, submodule_dir); + submodule_dir); print_verilog_submodule_muxes(module_manager, netlist_manager, mux_lib, circuit_lib, - verilog_dir, submodule_dir, + submodule_dir, fpga_verilog_opts.explicit_port_mapping()); /* LUTes */ print_verilog_submodule_luts(const_cast(module_manager), netlist_manager, circuit_lib, - verilog_dir, submodule_dir, + submodule_dir, fpga_verilog_opts.explicit_port_mapping()); /* Hard wires */ print_verilog_submodule_wires(const_cast(module_manager), netlist_manager, circuit_lib, - verilog_dir, submodule_dir); + submodule_dir); /* 4. Memories */ print_verilog_submodule_memories(const_cast(module_manager), netlist_manager, mux_lib, circuit_lib, - verilog_dir, submodule_dir, + submodule_dir, fpga_verilog_opts.explicit_port_mapping()); /* 5. Dump template for all the modules */ if (true == fpga_verilog_opts.print_user_defined_template()) { print_verilog_submodule_templates(const_cast(module_manager), circuit_lib, - verilog_dir, submodule_dir); + submodule_dir); } /* Create a header file to include all the subckts */ diff --git a/openfpga/src/fpga_verilog/verilog_submodule.h b/openfpga/src/fpga_verilog/verilog_submodule.h index d3de8b9d7..06bb7aeef 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule.h +++ b/openfpga/src/fpga_verilog/verilog_submodule.h @@ -20,7 +20,6 @@ void print_verilog_submodule(ModuleManager& module_manager, NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const FabricVerilogOption& fpga_verilog_opts); diff --git a/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp index b4255b3e9..faf965068 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp @@ -207,7 +207,6 @@ void print_one_verilog_template_module(const ModuleManager& module_manager, ********************************************************************/ void print_verilog_submodule_templates(const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir) { std::string verilog_fname(submodule_dir + USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME); @@ -223,8 +222,6 @@ void print_verilog_submodule_templates(const ModuleManager& module_manager, print_verilog_file_header(fp, "Template for user-defined Verilog modules"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Output essential models*/ for (const auto& model : circuit_lib.models()) { /* Focus on user-defined modules, which must have a Verilog netlist defined */ diff --git a/openfpga/src/fpga_verilog/verilog_submodule_utils.h b/openfpga/src/fpga_verilog/verilog_submodule_utils.h index fedcb63a8..3f0e1dadd 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule_utils.h +++ b/openfpga/src/fpga_verilog/verilog_submodule_utils.h @@ -29,7 +29,6 @@ void add_user_defined_verilog_modules(ModuleManager& module_manager, void print_verilog_submodule_templates(const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp index 9596f20a3..79c6ebebe 100644 --- a/openfpga/src/fpga_verilog/verilog_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp @@ -58,9 +58,6 @@ void print_verilog_top_module(NetlistManager& netlist_manager, print_verilog_file_header(fp, std::string("Top-level Verilog module for FPGA")); - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, top_module, use_explicit_mapping); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 25017d741..a477fa99e 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -799,7 +799,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, const VprNetlistAnnotation& netlist_annotation, const std::string& circuit_name, const std::string& verilog_fname, - const std::string& verilog_dir, const SimulationSetting& simulation_parameters) { std::string timer_message = std::string("Write autocheck testbench for FPGA top-level Verilog netlist for '") + circuit_name + std::string("'"); @@ -818,9 +817,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, std::string title = std::string("FPGA Verilog Testbench for Top-level netlist of Design: ") + circuit_name; print_verilog_file_header(fp, title); - /* Print preprocessing flags and external netlists */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Find the top_module */ ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name()); VTR_ASSERT(true == module_manager.valid_module_id(top_module)); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h index 5684b37e2..c0ad77c51 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.h +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h @@ -33,7 +33,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, const VprNetlistAnnotation& netlist_annotation, const std::string& circuit_name, const std::string& verilog_fname, - const std::string& verilog_dir, const SimulationSetting& simulation_parameters); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_wire.cpp b/openfpga/src/fpga_verilog/verilog_wire.cpp index d28b26f81..bb8419edd 100644 --- a/openfpga/src/fpga_verilog/verilog_wire.cpp +++ b/openfpga/src/fpga_verilog/verilog_wire.cpp @@ -95,7 +95,6 @@ void print_verilog_wire_module(const ModuleManager& module_manager, void print_verilog_submodule_wires(const ModuleManager& module_manager, NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir) { std::string verilog_fname(submodule_dir + std::string(WIRES_VERILOG_FILE_NAME)); @@ -111,8 +110,6 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager, print_verilog_file_header(fp, "Wires"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Print Verilog models for regular wires*/ print_verilog_comment(fp, std::string("----- BEGIN Verilog modules for regular wires -----")); for (const auto& model : circuit_lib.models_by_type(CIRCUIT_MODEL_WIRE)) { diff --git a/openfpga/src/fpga_verilog/verilog_wire.h b/openfpga/src/fpga_verilog/verilog_wire.h index 62331d8b9..d9996fbcf 100644 --- a/openfpga/src/fpga_verilog/verilog_wire.h +++ b/openfpga/src/fpga_verilog/verilog_wire.h @@ -21,7 +21,6 @@ namespace openfpga { void print_verilog_submodule_wires(const ModuleManager& module_manager, NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir); } /* end namespace openfpga */ From 9d1b3d68653bab45c4927a5c7f55551316a94cce Mon Sep 17 00:00:00 2001 From: ganeshgore Date: Fri, 24 Apr 2020 21:53:57 -0600 Subject: [PATCH 02/35] Fixed modelsim include references --- openfpga_flow/misc/modelsim_runsim.tcl | 12 +------ openfpga_flow/scripts/run_modelsim.py | 43 +++++++++++++++++++------- 2 files changed, 32 insertions(+), 23 deletions(-) diff --git a/openfpga_flow/misc/modelsim_runsim.tcl b/openfpga_flow/misc/modelsim_runsim.tcl index 64578d883..a7734bae0 100644 --- a/openfpga_flow/misc/modelsim_runsim.tcl +++ b/openfpga_flow/misc/modelsim_runsim.tcl @@ -11,27 +11,17 @@ set simtime ${SIMTIME} set unit ${UNIT} #Path were both tcl script are located -set verilog_path ${VERILOG_PATH} set project_path "${MODELSIM_PROJ_DIR}/msim_projects/" #Path were the verilog files are located -set verilog_path ${VERILOG_PATH} - -set verilog_files [list \ - ${VERILOG_PATH}${VERILOG_FILE1} \ - ${VERILOG_PATH}${VERILOG_FILE2} \ - ${VERILOG_PATH}fpga_defines.v - ] +set verilog_files ${VERILOG_PATH}/*_include_netlists_resolved.v #Source the tcl script source ${MODELSIM_PROJ_DIR}/${BENCHMARK}_autocheck_proc.tcl #Execute the top level procedure - try { top_create_new_project $$projectname $$verilog_files $$project_path $$simtime $$unit $$top_tb } finally { quit } - -#Relaunch simulation diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_modelsim.py index 077b84e61..564ca504d 100644 --- a/openfpga_flow/scripts/run_modelsim.py +++ b/openfpga_flow/scripts/run_modelsim.py @@ -104,7 +104,7 @@ def main(): logfile_path = os.path.join(gc["task_dir"], taskname, task_run, "modelsim_run.log") resultfile_path = os.path.join(gc["task_dir"], - taskname, task_run, "modelsim_result.csv") + taskname, task_run, "modelsim_result.csv") logfilefh = logging.FileHandler(logfile_path, "w") logfilefh.setFormatter(logging.Formatter(FILE_LOG_FORMAT)) logger.addHandler(logfilefh) @@ -129,7 +129,8 @@ def main(): task_ini_files.append(INIfile) logger.info(f"Found {len(task_ini_files)} INI files") results = create_tcl_script(task_ini_files) - collect_result(resultfile_path, results) + if args.run_sim: + collect_result(resultfile_path, results) def clean_up_and_exit(msg): @@ -168,7 +169,21 @@ def create_tcl_script(files): config["MODELSIM_PROJ_NAME"] = args.modelsim_proj_name config["MODELSIM_INI"] = args.modelsim_ini - + config["VERILOG_PATH"] = os.path.join( + os.getcwd(), config["VERILOG_PATH"]) + IncludeFile = os.path.join( + os.getcwd(), + config["VERILOG_PATH"], + config["VERILOG_FILE2"]) + IncludeFileResolved = os.path.join( + os.getcwd(), + config["VERILOG_PATH"], + config["VERILOG_FILE2"].replace(".v", "_resolved.v")) + with open(IncludeFileResolved, "w") as fpw: + with open(IncludeFile, "r") as fp: + for eachline in fp.readlines(): + eachline = eachline.replace("./SRC", "../../../SRC/") + fpw.write(eachline) # Modify the variables in config file here config["TOP_TB"] = os.path.splitext(config["TOP_TB"])[0] @@ -193,13 +208,13 @@ def create_tcl_script(files): "ini_file": eachFile, "modelsim_run_dir": args.modelsim_run_dir, "runsim_filename": runsim_filename, - "run_complete" :False, + "run_complete": False, "status": False, - "finished" : True, - "starttime" : 0, - "endtime" : 0, + "finished": True, + "starttime": 0, + "endtime": 0, "Errors": 0, - "Warnings" : 0 + "Warnings": 0 }) # Execute modelsim if args.run_sim: @@ -229,7 +244,7 @@ def run_modelsim_thread(s, eachJob, job_list): thread_name = threading.currentThread().getName() eachJob["starttime"] = time.time() eachJob["Errors"] = 0 - eachJob["Warnings"]= 0 + eachJob["Warnings"] = 0 try: logfile = "%s_modelsim.log" % thread_name eachJob["logfile"] = "" + \ @@ -248,7 +263,8 @@ def run_modelsim_thread(s, eachJob, job_list): for line in process.stdout: if "Errors" in line: logger.info(line.strip()) - e,w = re.match("# .*: ([0-9].*), .*: ([0-9].*)", line).groups() + e, w = re.match( + "# .*: ([0-9].*), .*: ([0-9].*)", line).groups() eachJob["Errors"] += int(e) eachJob["Warnings"] += int(w) sys.stdout.buffer.flush() @@ -275,8 +291,10 @@ def run_modelsim_thread(s, eachJob, job_list): no_of_finished_job = sum([not eachJ["finished"] for eachJ in job_list]) logger.info("***** %d runs pending *****" % (no_of_finished_job)) + def collect_result(result_file, result_obj): - colnames = ["status", "Errors", "Warnings", "run_complete", "exectime", "finished", "logfile"] + colnames = ["status", "Errors", "Warnings", + "run_complete", "exectime", "finished", "logfile"] if len(result_obj): with open(result_file, 'w', newline='') as csvfile: writer = csv.DictWriter( @@ -285,11 +303,12 @@ def collect_result(result_file, result_obj): for eachResult in result_obj: writer.writerow(eachResult) logger.info("= = = ="*10) - passed_jobs = [ each["status"] for each in result_obj ] + passed_jobs = [each["status"] for each in result_obj] logger.info(f"Passed Jobs %d/%d", len(passed_jobs), len(result_obj)) logger.info(f"Result file stored at {result_file}") logger.info("= = = ="*10) + if __name__ == "__main__": if args.debug: logger.info("Setting loggger in debug mode") From a3103f6afef43d85f6dc603460f415af727de645 Mon Sep 17 00:00:00 2001 From: ganeshgore Date: Sat, 25 Apr 2020 20:16:17 -0600 Subject: [PATCH 03/35] BugFix : Relative path for refrence benchmark fixed --- .../OpenFPGAShellScripts/mcnc_example_script.openfpga | 6 +++--- openfpga_flow/scripts/run_modelsim.py | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga index 9a4f577f8..ba086855e 100644 --- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga @@ -40,8 +40,8 @@ build_fabric_bitstream --verbose write_fabric_verilog --file ./SRC \ --explicit_port_mapping \ --include_timing \ - --include_signal_init - #--support_icarus_simulator + --include_signal_init + #--support_icarus_simulator # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC \ # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./simulation_deck_info.ini +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ./${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./simulation_deck_info.ini # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_modelsim.py index 564ca504d..4151ebd4b 100644 --- a/openfpga_flow/scripts/run_modelsim.py +++ b/openfpga_flow/scripts/run_modelsim.py @@ -182,7 +182,7 @@ def create_tcl_script(files): with open(IncludeFileResolved, "w") as fpw: with open(IncludeFile, "r") as fp: for eachline in fp.readlines(): - eachline = eachline.replace("./SRC", "../../../SRC/") + eachline = eachline.replace("\"./", "\"../../../") fpw.write(eachline) # Modify the variables in config file here config["TOP_TB"] = os.path.splitext(config["TOP_TB"])[0] From c1b73efa621c19a2fbb5ee86036a4e8ec68d8e8f Mon Sep 17 00:00:00 2001 From: ganeshgore Date: Wed, 10 Jun 2020 23:12:30 -0600 Subject: [PATCH 04/35] Added support for simulation setting file in the task flow --- openfpga_flow/scripts/run_fpga_flow.py | 3 ++ openfpga_flow/scripts/run_fpga_task.py | 2 + .../mcnc_big20/config/task.conf | 47 ++++++++++--------- 3 files changed, 29 insertions(+), 23 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index cee4ec2ce..fcf47ee44 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -83,6 +83,8 @@ parser.add_argument('--openfpga_shell_template', type=str, help="Sample openfpga shell script") parser.add_argument('--openfpga_arch_file', type=str, help="Openfpga architecture file for shell") +parser.add_argument('--openfpga_sim_setting_file', type=str, + help="Openfpga simulation file for shell") parser.add_argument('--yosys_tmpl', type=str, help="Alternate yosys template, generates top_module.blif") parser.add_argument('--disp', action="store_true", @@ -683,6 +685,7 @@ def run_openfpga_shell(): path_variables = script_env_vars["PATH"] path_variables["VPR_ARCH_FILE"] = args.arch_file path_variables["OPENFPGA_ARCH_FILE"] = args.openfpga_arch_file + path_variables["OPENFPGA_SIM_SETTING_FILE"] = args.openfpga_sim_setting_file path_variables["VPR_TESTBENCH_BLIF"] = args.top_module+".blif" path_variables["ACTIVITY_FILE"] = args.top_module+"_ace_out.act" path_variables["REFERENCE_VERILOG_TESTBENCH"] = args.top_module + \ diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 9567c4fe5..3361a3082 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -355,6 +355,8 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf): task_gc.get("openfpga_shell_template")] command += ["--openfpga_arch_file", task_gc.get("openfpga_arch_file")] + command += ["--openfpga_sim_setting_file", + task_gc.get("openfpga_sim_setting_file")] if benchmark_obj.get("activity_file"): command += ["--activity_file", benchmark_obj.get("activity_file")] diff --git a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf index 5028283fb..149c0695b 100644 --- a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf @@ -16,12 +16,13 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml [BENCHMARKS] -#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif +#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif #bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif #bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif ## VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file @@ -39,91 +40,91 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_ti #bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif #bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif ## Passed -bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif -#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif +bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif +# bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif #bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif #bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif #bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif #bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif [SYNTHESIS_PARAM] -# Benchmark alu4 +# Benchmark alu4 bench0_top = alu4 bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.act bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.v -# Benchmark apex2 +# Benchmark apex2 bench1_top = apex2 bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v -# Benchmark apex4 +# Benchmark apex4 bench2_top = apex4 bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.act bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.v -# Benchmark bigkey +# Benchmark bigkey bench3_top = bigkey bench3_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.act bench3_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.v -# Benchmark clma +# Benchmark clma bench4_top = clma bench4_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.act bench4_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.v -# Benchmark des +# Benchmark des bench5_top = des bench5_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.act bench5_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.v -# Benchmark diffeq +# Benchmark diffeq bench6_top = diffeq bench6_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.act bench6_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.v -# Benchmark dsip +# Benchmark dsip bench7_top = dsip bench7_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.act bench7_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.v -# Benchmark elliptic +# Benchmark elliptic bench8_top = elliptic bench8_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.act bench8_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.v -# Benchmark ex1010 +# Benchmark ex1010 bench9_top = ex1010 bench9_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.act bench9_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.v -# Benchmark ex5p +# Benchmark ex5p bench10_top = ex5p bench10_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.act bench10_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.v -# Benchmark frisc +# Benchmark frisc bench11_top = frisc bench11_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.act bench11_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.v -# Benchmark misex3 +# Benchmark misex3 bench12_top = misex3 bench12_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.act bench12_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.v -# Benchmark pdc +# Benchmark pdc bench13_top = pdc bench13_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.act bench13_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.v -# Benchmark s298 +# Benchmark s298 bench14_top = s298 bench14_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act bench14_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v -# Benchmark s38417 +# Benchmark s38417 bench15_top = s38417 bench15_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.act bench15_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.v -# Benchmark s38584 +# Benchmark s38584 bench16_top = s38584 bench16_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.act bench16_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.v -# Benchmark seq +# Benchmark seq bench17_top = seq bench17_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.act bench17_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.v -# Benchmark spla +# Benchmark spla bench18_top = spla bench18_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.act bench18_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.v -# Benchmark tseng +# Benchmark tseng bench19_top = tseng bench19_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.act bench19_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.v From 8a4ec85c39b38e2de2e3c6060cf2bc2969d0f1d8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 11 Jun 2020 21:44:25 -0600 Subject: [PATCH 05/35] add configurable children-related methods to module manager --- openfpga/src/fabric/module_manager.cpp | 22 ++++++++++++++++++++++ openfpga/src/fabric/module_manager.h | 12 ++++++++++++ 2 files changed, 34 insertions(+) diff --git a/openfpga/src/fabric/module_manager.cpp b/openfpga/src/fabric/module_manager.cpp index d03af54b0..3f5cfdbfb 100644 --- a/openfpga/src/fabric/module_manager.cpp +++ b/openfpga/src/fabric/module_manager.cpp @@ -626,6 +626,18 @@ void ModuleManager::add_configurable_child(const ModuleId& parent_module, configurable_child_instances_[parent_module].push_back(child_instance); } +void ModuleManager::reserve_configurable_child(const ModuleId& parent_module, + const size_t& num_children) { + VTR_ASSERT ( valid_module_id(parent_module) ); + /* Do reserve when the number of children is larger than current size of lists */ + if (num_children > configurable_children_[parent_module].size()) { + configurable_children_[parent_module].reserve(num_children); + } + if (num_children > configurable_child_instances_[parent_module].size()) { + configurable_child_instances_[parent_module].reserve(num_children); + } +} + /* Add a net to the connection graph of the module */ ModuleNetId ModuleManager::create_module_net(const ModuleId& module) { /* Validate the module id */ @@ -741,6 +753,16 @@ ModuleNetSinkId ModuleManager::add_module_net_sink(const ModuleId& module, const return net_sink; } +/****************************************************************************** + * Public Deconstructor + ******************************************************************************/ +void ModuleManager::clear_configurable_children(const ModuleId& parent_module) { + VTR_ASSERT(valid_module_id(parent_module)); + + configurable_children_[parent_module].clear(); + configurable_child_instances_[parent_module].clear(); +} + /****************************************************************************** * Private validators/invalidators ******************************************************************************/ diff --git a/openfpga/src/fabric/module_manager.h b/openfpga/src/fabric/module_manager.h index cd79bde8c..ee06f1415 100644 --- a/openfpga/src/fabric/module_manager.h +++ b/openfpga/src/fabric/module_manager.h @@ -156,6 +156,11 @@ class ModuleManager { void set_child_instance_name(const ModuleId& parent_module, const ModuleId& child_module, const size_t& instance_id, const std::string& instance_name); /* Add a configurable child module to module */ void add_configurable_child(const ModuleId& module, const ModuleId& child_module, const size_t& child_instance); + /* Reserved a number of configurable children + * for memory efficiency + */ + void reserve_configurable_child(const ModuleId& module, const size_t& num_children); + /* Add a net to the connection graph of the module */ ModuleNetId create_module_net(const ModuleId& module); /* Set the name of net */ @@ -169,6 +174,13 @@ class ModuleManager { ModuleNetSinkId add_module_net_sink(const ModuleId& module, const ModuleNetId& net, const ModuleId& sink_module, const size_t& instance_id, const ModulePortId& sink_port, const size_t& sink_pin); + public: /* Public deconstructors */ + /* This is a strong function which will remove all the configurable children + * under a given parent module + * It is mainly used by loading fabric keys + * Do NOT use unless you know what you are doing!!! + */ + void clear_configurable_children(const ModuleId& parent_module); public: /* Public validators/invalidators */ bool valid_module_id(const ModuleId& module) const; bool valid_module_port_id(const ModuleId& module, const ModulePortId& port) const; From 9167b288b68e70eeb1143529598189eb4ca552ad Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 11 Jun 2020 21:50:46 -0600 Subject: [PATCH 06/35] add options for fabric key --- openfpga/src/base/openfpga_setup_command.cpp | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp index bf2412a6f..5d50614ac 100644 --- a/openfpga/src/base/openfpga_setup_command.cpp +++ b/openfpga/src/base/openfpga_setup_command.cpp @@ -273,6 +273,17 @@ ShellCommandId add_openfpga_build_fabric_command(openfpga::Shell Date: Thu, 11 Jun 2020 23:59:24 -0600 Subject: [PATCH 07/35] bug fix for 'build_fabric' command --- openfpga/src/base/openfpga_setup_command.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp index 5d50614ac..ca5864b2e 100644 --- a/openfpga/src/base/openfpga_setup_command.cpp +++ b/openfpga/src/base/openfpga_setup_command.cpp @@ -274,11 +274,11 @@ ShellCommandId add_openfpga_build_fabric_command(openfpga::Shell Date: Fri, 12 Jun 2020 00:07:04 -0600 Subject: [PATCH 08/35] add fabric key library --- libopenfpga/CMakeLists.txt | 1 + .../libarchopenfpga/src/write_xml_utils.cpp | 15 ++++ .../libarchopenfpga/src/write_xml_utils.h | 4 + libopenfpga/libfabrickey/CMakeLists.txt | 35 ++++++++ .../libfabrickey/key_examples/key_example.xml | 7 ++ libopenfpga/libfabrickey/src/fabric_key.cpp | 82 +++++++++++++++++ libopenfpga/libfabrickey/src/fabric_key.h | 59 +++++++++++++ libopenfpga/libfabrickey/src/fabric_key_fwd.h | 22 +++++ .../libfabrickey/src/read_xml_fabric_key.cpp | 88 +++++++++++++++++++ .../libfabrickey/src/read_xml_fabric_key.h | 16 ++++ .../libfabrickey/src/write_xml_fabric_key.cpp | 69 +++++++++++++++ .../libfabrickey/src/write_xml_fabric_key.h | 16 ++++ .../libfabrickey/test/test_fabric_key.cpp | 34 +++++++ 13 files changed, 448 insertions(+) create mode 100644 libopenfpga/libfabrickey/CMakeLists.txt create mode 100644 libopenfpga/libfabrickey/key_examples/key_example.xml create mode 100644 libopenfpga/libfabrickey/src/fabric_key.cpp create mode 100644 libopenfpga/libfabrickey/src/fabric_key.h create mode 100644 libopenfpga/libfabrickey/src/fabric_key_fwd.h create mode 100644 libopenfpga/libfabrickey/src/read_xml_fabric_key.cpp create mode 100644 libopenfpga/libfabrickey/src/read_xml_fabric_key.h create mode 100644 libopenfpga/libfabrickey/src/write_xml_fabric_key.cpp create mode 100644 libopenfpga/libfabrickey/src/write_xml_fabric_key.h create mode 100644 libopenfpga/libfabrickey/test/test_fabric_key.cpp diff --git a/libopenfpga/CMakeLists.txt b/libopenfpga/CMakeLists.txt index 00cf0acf0..ec3299198 100644 --- a/libopenfpga/CMakeLists.txt +++ b/libopenfpga/CMakeLists.txt @@ -3,3 +3,4 @@ add_subdirectory(libini) add_subdirectory(libopenfpgashell) add_subdirectory(libarchopenfpga) add_subdirectory(libopenfpgautil) +add_subdirectory(libfabrickey) diff --git a/libopenfpga/libarchopenfpga/src/write_xml_utils.cpp b/libopenfpga/libarchopenfpga/src/write_xml_utils.cpp index e4d32e720..a416203ee 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_utils.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_utils.cpp @@ -61,6 +61,21 @@ void write_xml_attribute(std::fstream& fp, fp << "\""; } +/******************************************************************** + * A most utilized function to write an XML attribute to file + * This accepts the value as a size_t + *******************************************************************/ +void write_xml_attribute(std::fstream& fp, + const char* attr, + const size_t& value) { + /* Validate the file stream */ + openfpga::valid_file_stream(fp); + + fp << " " << attr << "=\""; + fp << value; + fp << "\""; +} + /******************************************************************** * A most utilized function to write an XML attribute to file * This accepts the value as a float diff --git a/libopenfpga/libarchopenfpga/src/write_xml_utils.h b/libopenfpga/libarchopenfpga/src/write_xml_utils.h index 3976d78b9..b54caf6db 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_utils.h +++ b/libopenfpga/libarchopenfpga/src/write_xml_utils.h @@ -26,4 +26,8 @@ void write_xml_attribute(std::fstream& fp, const char* attr, const float& value); +void write_xml_attribute(std::fstream& fp, + const char* attr, + const size_t& value); + #endif diff --git a/libopenfpga/libfabrickey/CMakeLists.txt b/libopenfpga/libfabrickey/CMakeLists.txt new file mode 100644 index 000000000..db52b510e --- /dev/null +++ b/libopenfpga/libfabrickey/CMakeLists.txt @@ -0,0 +1,35 @@ +cmake_minimum_required(VERSION 3.9) + +project("libfabrickey") + +file(GLOB_RECURSE EXEC_SOURCES test/*.cpp) +file(GLOB_RECURSE LIB_SOURCES src/*.cpp) +file(GLOB_RECURSE LIB_HEADERS src/*.h) +files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS) + +#Remove test executable from library +list(REMOVE_ITEM LIB_SOURCES ${EXEC_SOURCES}) + +#Create the library +add_library(libfabrickey STATIC + ${LIB_HEADERS} + ${LIB_SOURCES}) +target_include_directories(libfabrickey PUBLIC ${LIB_INCLUDE_DIRS}) +set_target_properties(libfabrickey PROPERTIES PREFIX "") #Avoid extra 'lib' prefix + +#Specify link-time dependancies +target_link_libraries(libfabrickey + libopenfpgautil + libarchopenfpga + libvtrutil + libpugixml + libpugiutil) + +#Create the test executable +foreach(testsourcefile ${EXEC_SOURCES}) + # Use a simple string replace, to cut off .cpp. + get_filename_component(testname ${testsourcefile} NAME_WE) + add_executable(${testname} ${testsourcefile}) + # Make sure the library is linked to each test executable + target_link_libraries(${testname} libfabrickey) +endforeach(testsourcefile ${EXEC_SOURCES}) diff --git a/libopenfpga/libfabrickey/key_examples/key_example.xml b/libopenfpga/libfabrickey/key_examples/key_example.xml new file mode 100644 index 000000000..49140b6e0 --- /dev/null +++ b/libopenfpga/libfabrickey/key_examples/key_example.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/libopenfpga/libfabrickey/src/fabric_key.cpp b/libopenfpga/libfabrickey/src/fabric_key.cpp new file mode 100644 index 000000000..187150800 --- /dev/null +++ b/libopenfpga/libfabrickey/src/fabric_key.cpp @@ -0,0 +1,82 @@ +#include "vtr_assert.h" + +#include "fabric_key.h" + +/************************************************************************ + * Member functions for class FabricKey + ***********************************************************************/ + +/************************************************************************ + * Constructors + ***********************************************************************/ +FabricKey::FabricKey() { + return; +} + +/************************************************************************ + * Public Accessors : aggregates + ***********************************************************************/ +FabricKey::fabric_key_range FabricKey::keys() const { + return vtr::make_range(key_ids_.begin(), key_ids_.end()); +} + +/************************************************************************ + * Public Accessors : Basic data query + ***********************************************************************/ +/* Access the name of a key */ +std::string FabricKey::key_name(const FabricKeyId& key_id) const { + /* validate the key_id */ + VTR_ASSERT(valid_key_id(key_id)); + return key_names_[key_id]; +} + +/* Access the value of a key */ +size_t FabricKey::key_value(const FabricKeyId& key_id) const { + /* validate the key_id */ + VTR_ASSERT(valid_key_id(key_id)); + return key_values_[key_id]; +} + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +void FabricKey::reserve_keys(const size_t& num_keys) { + key_ids_.reserve(num_keys); + key_names_.reserve(num_keys); + key_values_.reserve(num_keys); +} + +/* Create a new key and add it to the library, return an id */ +FabricKeyId FabricKey::create_key() { + /* Create a new id */ + FabricKeyId key = FabricKeyId(key_ids_.size()); + key_ids_.push_back(key); + key_names_.emplace_back(); + key_values_.emplace_back(); + + return key; +} + +void FabricKey::set_key_name(const FabricKeyId& key_id, + const std::string& name) { + /* validate the key_id */ + VTR_ASSERT(valid_key_id(key_id)); + + key_names_[key_id] = name; +} + +void FabricKey::set_key_value(const FabricKeyId& key_id, + const size_t& value) { + /* validate the key_id */ + VTR_ASSERT(valid_key_id(key_id)); + + key_values_[key_id] = value; +} + +/************************************************************************ + * Internal invalidators/validators + ***********************************************************************/ +/* Validators */ +bool FabricKey::valid_key_id(const FabricKeyId& key_id) const { + return ( size_t(key_id) < key_ids_.size() ) && ( key_id == key_ids_[key_id] ); +} diff --git a/libopenfpga/libfabrickey/src/fabric_key.h b/libopenfpga/libfabrickey/src/fabric_key.h new file mode 100644 index 000000000..7488923df --- /dev/null +++ b/libopenfpga/libfabrickey/src/fabric_key.h @@ -0,0 +1,59 @@ +#ifndef FABRIC_KEY_H +#define FABRIC_KEY_H + +/******************************************************************** + * This file include the declaration of fabric key + *******************************************************************/ +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_vector.h" + +#include "fabric_key_fwd.h" + +/******************************************************************** + * A data structure to describe a secure key for fabric organization + * + * Typical usage: + * -------------- + * // Create an empty fabric key + * FabricKey fabric_key; + * // Add a key with name and value + * FabricKeyId key = fabic_key.create_key(key_name, key_value); + * + *******************************************************************/ +class FabricKey { + public: /* Types */ + typedef vtr::vector::const_iterator fabric_key_iterator; + /* Create range */ + typedef vtr::Range fabric_key_range; + public: /* Constructors */ + FabricKey(); + public: /* Accessors: aggregates */ + fabric_key_range keys() const; + public: /* Public Accessors: Basic data query */ + std::string key_name(const FabricKeyId& key_id) const; + size_t key_value(const FabricKeyId& key_id) const; + public: /* Public Mutators: model-related */ + void reserve_keys(const size_t& num_keys); + FabricKeyId create_key(); + void set_key_name(const FabricKeyId& key_id, + const std::string& name); + void set_key_value(const FabricKeyId& key_id, + const size_t& value); + public: /* Public invalidators/validators */ + bool valid_key_id(const FabricKeyId& key_id) const; + private: /* Internal data */ + /* Unique ids for each key */ + vtr::vector key_ids_; + + /* Names for each key */ + vtr::vector key_names_; + + /* Values for each key */ + vtr::vector key_values_; +}; + +#endif diff --git a/libopenfpga/libfabrickey/src/fabric_key_fwd.h b/libopenfpga/libfabrickey/src/fabric_key_fwd.h new file mode 100644 index 000000000..523eaeab8 --- /dev/null +++ b/libopenfpga/libfabrickey/src/fabric_key_fwd.h @@ -0,0 +1,22 @@ +/************************************************************************ + * A header file for FabricKey class, including critical data declaration + * Please include this file only for using any TechnologyLibrary data structure + * Refer to fabric_key.h for more details + ***********************************************************************/ + +/************************************************************************ + * Create strong id for FabricKey to avoid illegal type casting + ***********************************************************************/ +#ifndef FABRIC_KEY_FWD_H +#define FABRIC_KEY_FWD_H + +#include "vtr_strong_id.h" + +struct fabric_key_id_tag; + +typedef vtr::StrongId FabricKeyId; + +/* Short declaration of class */ +class FabricKey; + +#endif diff --git a/libopenfpga/libfabrickey/src/read_xml_fabric_key.cpp b/libopenfpga/libfabrickey/src/read_xml_fabric_key.cpp new file mode 100644 index 000000000..8b1f03f11 --- /dev/null +++ b/libopenfpga/libfabrickey/src/read_xml_fabric_key.cpp @@ -0,0 +1,88 @@ +/******************************************************************** + * This file includes the top-level function of this library + * which reads an XML of a fabric key to the associated + * data structures + *******************************************************************/ +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "read_xml_util.h" + +#include "read_xml_fabric_key.h" + +/******************************************************************** + * Parse XML codes of a to an object of FabricKey + *******************************************************************/ +static +void read_xml_component_key(pugi::xml_node& xml_component_key, + const pugiutil::loc_data& loc_data, + FabricKey& fabric_key) { + + /* Find the id of component key */ + const size_t& id = get_attribute(xml_component_key, "id", loc_data).as_int(); + const std::string& name = get_attribute(xml_component_key, "name", loc_data).as_string(); + const size_t& value = get_attribute(xml_component_key, "value", loc_data).as_int(); + + if (false == fabric_key.valid_key_id(FabricKeyId(id))) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_component_key), + "Invalid 'id' attribute '%d'\n", + id); + } + + VTR_ASSERT_SAFE(true == fabric_key.valid_key_id(FabricKeyId(id))); + + fabric_key.set_key_name(FabricKeyId(id), name); + fabric_key.set_key_value(FabricKeyId(id), value); +} + +/******************************************************************** + * Parse XML codes about to an object of FabricKey + *******************************************************************/ +FabricKey read_xml_fabric_key(const char* key_fname) { + + vtr::ScopedStartFinishTimer timer("Read Fabric Key"); + + FabricKey fabric_key; + + /* Parse the file */ + pugi::xml_document doc; + pugiutil::loc_data loc_data; + + try { + loc_data = pugiutil::load_xml(doc, key_fname); + + pugi::xml_node xml_root = get_single_child(doc, "fabric_key", loc_data); + + size_t num_keys = std::distance(xml_root.children().begin(), xml_root.children().end()); + fabric_key.reserve_keys(num_keys); + for (size_t ikey = 0; ikey < num_keys; ++ikey) { + fabric_key.create_key(); + } + + /* Iterate over the children under this node, + * each child should be named after circuit_model + */ + for (pugi::xml_node xml_key : xml_root.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_key.name() != std::string("key")) { + bad_tag(xml_key, loc_data, xml_root, {"key"}); + } + read_xml_component_key(xml_key, loc_data, fabric_key); + } + } catch (pugiutil::XmlError& e) { + archfpga_throw(key_fname, e.line(), + "%s", e.what()); + } + + return fabric_key; +} + diff --git a/libopenfpga/libfabrickey/src/read_xml_fabric_key.h b/libopenfpga/libfabrickey/src/read_xml_fabric_key.h new file mode 100644 index 000000000..692722d08 --- /dev/null +++ b/libopenfpga/libfabrickey/src/read_xml_fabric_key.h @@ -0,0 +1,16 @@ +#ifndef READ_XML_FABRIC_KEY_H +#define READ_XML_FABRIC_KEY_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "pugixml_util.hpp" +#include "pugixml.hpp" +#include "fabric_key.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ +FabricKey read_xml_fabric_key(const char* key_fname); + +#endif diff --git a/libopenfpga/libfabrickey/src/write_xml_fabric_key.cpp b/libopenfpga/libfabrickey/src/write_xml_fabric_key.cpp new file mode 100644 index 000000000..d384d8607 --- /dev/null +++ b/libopenfpga/libfabrickey/src/write_xml_fabric_key.cpp @@ -0,0 +1,69 @@ +/******************************************************************** + * This file includes functions that outputs a configuration protocol to XML format + *******************************************************************/ +/* Headers from system goes first */ +#include +#include + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" +#include "openfpga_digest.h" + +/* Headers from arch openfpga library */ +#include "write_xml_utils.h" + +/* Headers from fabrickey library */ +#include "write_xml_fabric_key.h" + +/******************************************************************** + * A writer to output a component key to XML format + *******************************************************************/ +static +void write_xml_fabric_component_key(std::fstream& fp, + const char* fname, + const FabricKey& fabric_key, + const FabricKeyId& component_key) { + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + fp << "\t" << "" << "\n"; +} + +/******************************************************************** + * A writer to output a fabric key to XML format + *******************************************************************/ +void write_xml_fabric_key(const char* fname, + const FabricKey& fabric_key) { + + vtr::ScopedStartFinishTimer timer("Write Fabric Key"); + + /* Create a file handler */ + std::fstream fp; + /* Open the file stream */ + fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + /* Write the root node */ + fp << "" << "\n"; + + /* Write component by component */ + for (const FabricKeyId& key : fabric_key.keys()) { + write_xml_fabric_component_key(fp, fname, fabric_key, key); + } + + /* Finish writing the root node */ + fp << "" << "\n"; + + /* Close the file stream */ + fp.close(); +} diff --git a/libopenfpga/libfabrickey/src/write_xml_fabric_key.h b/libopenfpga/libfabrickey/src/write_xml_fabric_key.h new file mode 100644 index 000000000..f47c39a12 --- /dev/null +++ b/libopenfpga/libfabrickey/src/write_xml_fabric_key.h @@ -0,0 +1,16 @@ +#ifndef WRITE_XML_FABRIC_KEY_H +#define WRITE_XML_FABRIC_KEY_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include "fabric_key.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ +void write_xml_fabric_key(const char* fname, + const FabricKey& fabric_key); + +#endif diff --git a/libopenfpga/libfabrickey/test/test_fabric_key.cpp b/libopenfpga/libfabrickey/test/test_fabric_key.cpp new file mode 100644 index 000000000..51acfd818 --- /dev/null +++ b/libopenfpga/libfabrickey/test/test_fabric_key.cpp @@ -0,0 +1,34 @@ +/******************************************************************** + * Unit test functions to validate the correctness of + * 1. parser of data structures + * 2. writer of data structures + *******************************************************************/ +/* Headers from vtrutils */ +#include "vtr_assert.h" +#include "vtr_log.h" + +/* Headers from fabric key */ +#include "read_xml_fabric_key.h" +#include "write_xml_fabric_key.h" + +int main(int argc, const char** argv) { + /* Ensure we have only one or two argument */ + VTR_ASSERT((2 == argc) || (3 == argc)); + + + /* Parse the fabric key from an XML file */ + FabricKey test_key = read_xml_fabric_key(argv[1]); + VTR_LOG("Read the fabric key from an XML file: %s.\n", + argv[1]); + + /* Output the circuit library to an XML file + * This is optional only used when there is a second argument + */ + if (3 <= argc) { + write_xml_fabric_key(argv[2], test_key); + VTR_LOG("Echo the fabric key to an XML file: %s.\n", + argv[2]); + } +} + + From 3499b4d3e76417e9e1494c59e40063f7b1f56d7f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 12 Jun 2020 10:41:34 -0600 Subject: [PATCH 09/35] add fabric key writer for top-level module --- .../libfabrickey/src/write_xml_fabric_key.cpp | 38 +++++++-- .../libfabrickey/src/write_xml_fabric_key.h | 4 +- openfpga/CMakeLists.txt | 1 + openfpga/src/base/openfpga_build_fabric.cpp | 12 +++ openfpga/src/fabric/fabric_key_writer.cpp | 80 +++++++++++++++++++ openfpga/src/fabric/fabric_key_writer.h | 23 ++++++ 6 files changed, 148 insertions(+), 10 deletions(-) create mode 100644 openfpga/src/fabric/fabric_key_writer.cpp create mode 100644 openfpga/src/fabric/fabric_key_writer.h diff --git a/libopenfpga/libfabrickey/src/write_xml_fabric_key.cpp b/libopenfpga/libfabrickey/src/write_xml_fabric_key.cpp index d384d8607..1697f94a6 100644 --- a/libopenfpga/libfabrickey/src/write_xml_fabric_key.cpp +++ b/libopenfpga/libfabrickey/src/write_xml_fabric_key.cpp @@ -19,29 +19,44 @@ /******************************************************************** * A writer to output a component key to XML format + * + * Return 0 if successful + * Return 1 if there are more serious bugs in the architecture + * Return 2 if fail when creating files *******************************************************************/ static -void write_xml_fabric_component_key(std::fstream& fp, - const char* fname, - const FabricKey& fabric_key, - const FabricKeyId& component_key) { +int write_xml_fabric_component_key(std::fstream& fp, + const FabricKey& fabric_key, + const FabricKeyId& component_key) { /* Validate the file stream */ - openfpga::check_file_stream(fname, fp); + if (false == openfpga::valid_file_stream(fp)) { + return 2; + } fp << "\t" << "" << "\n"; + + return 0; } /******************************************************************** * A writer to output a fabric key to XML format + * + * Return 0 if successful + * Return 1 if there are more serious bugs in the architecture + * Return 2 if fail when creating files *******************************************************************/ -void write_xml_fabric_key(const char* fname, - const FabricKey& fabric_key) { +int write_xml_fabric_key(const char* fname, + const FabricKey& fabric_key) { vtr::ScopedStartFinishTimer timer("Write Fabric Key"); @@ -56,9 +71,14 @@ void write_xml_fabric_key(const char* fname, /* Write the root node */ fp << "" << "\n"; + int err_code = 0; + /* Write component by component */ for (const FabricKeyId& key : fabric_key.keys()) { - write_xml_fabric_component_key(fp, fname, fabric_key, key); + err_code = write_xml_fabric_component_key(fp, fabric_key, key); + if (0 != err_code) { + return err_code; + } } /* Finish writing the root node */ @@ -66,4 +86,6 @@ void write_xml_fabric_key(const char* fname, /* Close the file stream */ fp.close(); + + return err_code; } diff --git a/libopenfpga/libfabrickey/src/write_xml_fabric_key.h b/libopenfpga/libfabrickey/src/write_xml_fabric_key.h index f47c39a12..985662abf 100644 --- a/libopenfpga/libfabrickey/src/write_xml_fabric_key.h +++ b/libopenfpga/libfabrickey/src/write_xml_fabric_key.h @@ -10,7 +10,7 @@ /******************************************************************** * Function declaration *******************************************************************/ -void write_xml_fabric_key(const char* fname, - const FabricKey& fabric_key); +int write_xml_fabric_key(const char* fname, + const FabricKey& fabric_key); #endif diff --git a/openfpga/CMakeLists.txt b/openfpga/CMakeLists.txt index 1cdd56a32..7578630af 100644 --- a/openfpga/CMakeLists.txt +++ b/openfpga/CMakeLists.txt @@ -22,6 +22,7 @@ target_link_libraries(libopenfpga libarchopenfpga libopenfpgashell libopenfpgautil + libfabrickey libini libvtrutil libvpr8) diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp index b1a1fe118..a5cb3125d 100644 --- a/openfpga/src/base/openfpga_build_fabric.cpp +++ b/openfpga/src/base/openfpga_build_fabric.cpp @@ -12,6 +12,7 @@ #include "device_rr_gsb_utils.h" #include "build_device_module.h" #include "fabric_hierarchy_writer.h" +#include "fabric_key_writer.h" #include "openfpga_build_fabric.h" /* Include global variables of VPR */ @@ -65,6 +66,7 @@ int build_fabric(OpenfpgaContext& openfpga_ctx, CommandOptionId opt_compress_routing = cmd.option("compress_routing"); CommandOptionId opt_duplicate_grid_pin = cmd.option("duplicate_grid_pin"); + CommandOptionId opt_write_fabric_key = cmd.option("write_fabric_key"); CommandOptionId opt_verbose = cmd.option("verbose"); if (true == cmd_context.option_enable(cmd, opt_compress_routing)) { @@ -83,6 +85,16 @@ int build_fabric(OpenfpgaContext& openfpga_ctx, cmd_context.option_enable(cmd, opt_duplicate_grid_pin), cmd_context.option_enable(cmd, opt_verbose)); + /* Output fabric key if user requested */ + if (true == cmd_context.option_enable(cmd, opt_write_fabric_key)) { + std::string fkey_fname = cmd_context.option_value(cmd, opt_write_fabric_key); + VTR_ASSERT(false == fkey_fname.empty()); + write_fabric_key_to_xml_file(openfpga_ctx.module_graph(), + fkey_fname, + cmd_context.option_enable(cmd, opt_verbose)); + + } + /* TODO: should identify the error code from internal function execution */ return CMD_EXEC_SUCCESS; } diff --git a/openfpga/src/fabric/fabric_key_writer.cpp b/openfpga/src/fabric/fabric_key_writer.cpp new file mode 100644 index 000000000..17f951ba2 --- /dev/null +++ b/openfpga/src/fabric/fabric_key_writer.cpp @@ -0,0 +1,80 @@ +/*************************************************************************************** + * Output fabric key of Module Graph to file formats + ***************************************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_log.h" +#include "vtr_assert.h" +#include "vtr_time.h" + +/* Headers from openfpgautil library */ +#include "openfpga_digest.h" + +/* Headers from archopenfpga library */ +#include "write_xml_fabric_key.h" + +#include "openfpga_naming.h" + +#include "fabric_key_writer.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/*************************************************************************************** + * Write the fabric key of top module to an XML file + * We will use the writer API in libfabrickey + * + * Return 0 if successful + * Return 1 if there are more serious bugs in the architecture + * Return 2 if fail when creating files + ***************************************************************************************/ +int write_fabric_key_to_xml_file(const ModuleManager& module_manager, + const std::string& fname, + const bool& verbose) { + std::string timer_message = std::string("Write fabric key to XML file '") + fname + std::string("'"); + + std::string dir_path = format_dir_path(find_path_dir_name(fname)); + + /* Create directories */ + create_directory(dir_path); + + /* Start time count */ + vtr::ScopedStartFinishTimer timer(timer_message); + + /* Use default name if user does not provide one */ + VTR_ASSERT(true != fname.empty()); + + /* Find top-level module */ + std::string top_module_name = generate_fpga_top_module_name(); + ModuleId top_module = module_manager.find_module(top_module_name); + if (true != module_manager.valid_module_id(top_module)) { + VTR_LOGV_ERROR(verbose, + "Unable to find the top-level module '%s'!\n", + top_module_name.c_str()); + return 1; + } + + /* Build a fabric key database by visiting all the configurable children */ + FabricKey fabric_key; + const size_t& num_keys = module_manager.configurable_children(top_module).size(); + fabric_key.reserve_keys(num_keys); + + for (size_t ichild = 0; ichild < num_keys; ++ichild) { + const ModuleId& child_module = module_manager.configurable_children(top_module)[ichild]; + const size_t& child_instance = module_manager.configurable_child_instances(top_module)[ichild]; + + FabricKeyId key = fabric_key.create_key(); + fabric_key.set_key_name(key, module_manager.module_name(child_module)); + fabric_key.set_key_value(key, child_instance); + } + + VTR_LOGV(verbose, + "Created %lu keys for the top module %s.\n", + num_keys, top_module_name.c_str()); + + /* Call the XML writer for fabric key */ + int err_code = write_xml_fabric_key(fname.c_str(), fabric_key); + + return err_code; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/fabric/fabric_key_writer.h b/openfpga/src/fabric/fabric_key_writer.h new file mode 100644 index 000000000..68e6468b2 --- /dev/null +++ b/openfpga/src/fabric/fabric_key_writer.h @@ -0,0 +1,23 @@ +#ifndef FABRIC_KEY_WRITER_H +#define FABRIC_KEY_WRITER_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "vpr_context.h" +#include "openfpga_context.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +int write_fabric_key_to_xml_file(const ModuleManager& module_manager, + const std::string& fname, + const bool& verbose); + +} /* end namespace openfpga */ + +#endif From cf9c3b0f4456e20a292781061cabb83756468560 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 12 Jun 2020 10:50:23 -0600 Subject: [PATCH 10/35] add write fabric to test cases --- openfpga/src/fabric/fabric_key_writer.cpp | 6 +++--- .../generate_fabric_example_script.openfpga | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga/src/fabric/fabric_key_writer.cpp b/openfpga/src/fabric/fabric_key_writer.cpp index 17f951ba2..40770965f 100644 --- a/openfpga/src/fabric/fabric_key_writer.cpp +++ b/openfpga/src/fabric/fabric_key_writer.cpp @@ -55,12 +55,12 @@ int write_fabric_key_to_xml_file(const ModuleManager& module_manager, /* Build a fabric key database by visiting all the configurable children */ FabricKey fabric_key; - const size_t& num_keys = module_manager.configurable_children(top_module).size(); + size_t num_keys = module_manager.configurable_children(top_module).size(); fabric_key.reserve_keys(num_keys); for (size_t ichild = 0; ichild < num_keys; ++ichild) { - const ModuleId& child_module = module_manager.configurable_children(top_module)[ichild]; - const size_t& child_instance = module_manager.configurable_child_instances(top_module)[ichild]; + ModuleId child_module = module_manager.configurable_children(top_module)[ichild]; + size_t child_instance = module_manager.configurable_child_instances(top_module)[ichild]; FabricKeyId key = fabric_key.create_key(); fabric_key.set_key_name(key, module_manager.module_name(child_module)); diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga index 38ebc9d28..d7f025434 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga @@ -18,7 +18,7 @@ check_netlist_naming_conflict --fix --report ./netlist_renaming.xml # Build the module graph # - Enabled compression on routing architecture modules # - Enable pin duplication on grid modules -build_fabric --compress_routing #--verbose +build_fabric --compress_routing --write_fabric_key ./fabric_key.xml #--verbose # Write the fabric hierarchy of module graph to a file # This is used by hierarchical PnR flows From 9dbf5363068808d03bdf894b582870265ec5103d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 12 Jun 2020 11:16:53 -0600 Subject: [PATCH 11/35] add shuffled configurable children support for top module --- openfpga/src/base/openfpga_build_fabric.cpp | 2 ++ openfpga/src/fabric/build_device_module.cpp | 3 +- openfpga/src/fabric/build_device_module.h | 1 + openfpga/src/fabric/build_top_module.cpp | 8 ++++- openfpga/src/fabric/build_top_module.h | 3 +- .../src/fabric/build_top_module_memory.cpp | 35 +++++++++++++++++++ openfpga/src/fabric/build_top_module_memory.h | 3 ++ 7 files changed, 52 insertions(+), 3 deletions(-) diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp index a5cb3125d..f5c007a09 100644 --- a/openfpga/src/base/openfpga_build_fabric.cpp +++ b/openfpga/src/base/openfpga_build_fabric.cpp @@ -66,6 +66,7 @@ int build_fabric(OpenfpgaContext& openfpga_ctx, CommandOptionId opt_compress_routing = cmd.option("compress_routing"); CommandOptionId opt_duplicate_grid_pin = cmd.option("duplicate_grid_pin"); + CommandOptionId opt_gen_random_fabric_key = cmd.option("generate_random_fabric_key"); CommandOptionId opt_write_fabric_key = cmd.option("write_fabric_key"); CommandOptionId opt_verbose = cmd.option("verbose"); @@ -83,6 +84,7 @@ int build_fabric(OpenfpgaContext& openfpga_ctx, g_vpr_ctx.device(), cmd_context.option_enable(cmd, opt_compress_routing), cmd_context.option_enable(cmd, opt_duplicate_grid_pin), + cmd_context.option_enable(cmd, opt_gen_random_fabric_key), cmd_context.option_enable(cmd, opt_verbose)); /* Output fabric key if user requested */ diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 4b2375057..36769636a 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -32,6 +32,7 @@ ModuleManager build_device_module_graph(IoLocationMap& io_location_map, const DeviceContext& vpr_device_ctx, const bool& compress_routing, const bool& duplicate_grid_pin, + const bool& generate_random_fabric_key, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build fabric module graph"); @@ -116,7 +117,7 @@ ModuleManager build_device_module_graph(IoLocationMap& io_location_map, openfpga_ctx.arch().arch_direct, openfpga_ctx.arch().config_protocol.type(), sram_model, - compress_routing, duplicate_grid_pin); + compress_routing, duplicate_grid_pin, generate_random_fabric_key); /* Now a critical correction has to be done! * In the module construction, we always use prefix of ports because they are binded diff --git a/openfpga/src/fabric/build_device_module.h b/openfpga/src/fabric/build_device_module.h index 75a9f982c..7b8a6bd2b 100644 --- a/openfpga/src/fabric/build_device_module.h +++ b/openfpga/src/fabric/build_device_module.h @@ -20,6 +20,7 @@ ModuleManager build_device_module_graph(IoLocationMap& io_location_map, const DeviceContext& vpr_device_ctx, const bool& compress_routing, const bool& duplicate_grid_pin, + const bool& generate_random_fabric_key, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 762ba66f0..a751834ef 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -321,7 +321,8 @@ void build_top_module(ModuleManager& module_manager, const e_config_protocol_type& sram_orgz_type, const CircuitModelId& sram_model, const bool& compact_routing_hierarchy, - const bool& duplicate_grid_pin) { + const bool& duplicate_grid_pin, + const bool& generate_random_fabric_key) { vtr::ScopedStartFinishTimer timer("Build FPGA fabric module"); @@ -369,6 +370,11 @@ void build_top_module(ModuleManager& module_manager, device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy); + /* Shuffle the configurable children in a random sequence */ + if (true == generate_random_fabric_key) { + shuffle_top_module_configurable_children(module_manager, top_module); + } + /* Add shared SRAM ports from the sub-modules under this Verilog module * This is a much easier job after adding sub modules (instances), * we just need to find all the I/O ports from the child modules and build a list of it diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h index d64de2755..fca3ea841 100644 --- a/openfpga/src/fabric/build_top_module.h +++ b/openfpga/src/fabric/build_top_module.h @@ -36,7 +36,8 @@ void build_top_module(ModuleManager& module_manager, const e_config_protocol_type& sram_orgz_type, const CircuitModelId& sram_model, const bool& compact_routing_hierarchy, - const bool& duplicate_grid_pin); + const bool& duplicate_grid_pin, + const bool& generate_random_fabric_key); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 6466d98e5..2ac546218 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -366,6 +366,41 @@ void organize_top_module_memory_modules(ModuleManager& module_manager, } } + +/******************************************************************** + * Shuffle the configurable children in a random sequence + * + * TODO: May use a more customized shuffle mechanism + * + * Note: + * - This function should NOT be called + * before allocating any configurable child + ********************************************************************/ +void shuffle_top_module_configurable_children(ModuleManager& module_manager, + const ModuleId& top_module) { + size_t num_keys = module_manager.configurable_children(top_module).size(); + std::vector shuffled_keys; + shuffled_keys.reserve(num_keys); + for (size_t ikey = 0; ikey < num_keys; ++ikey) { + shuffled_keys.push_back(ikey); + } + + std::random_shuffle(shuffled_keys.begin(), shuffled_keys.end()); + + /* Cache the configurable children and their instances */ + std::vector orig_configurable_children = module_manager.configurable_children(top_module); + std::vector orig_configurable_child_instances = module_manager.configurable_child_instances(top_module); + + /* Reorganize the configurable children */ + module_manager.clear_configurable_children(top_module); + + for (size_t ikey = 0; ikey < num_keys; ++ikey) { + module_manager.add_configurable_child(top_module, + orig_configurable_children[shuffled_keys[ikey]], + orig_configurable_child_instances[shuffled_keys[ikey]]); + } +} + /******************************************************************** * Add a list of ports that are used for SRAM configuration to the FPGA * top-level module diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h index b67389790..1c6dd56e5 100644 --- a/openfpga/src/fabric/build_top_module_memory.h +++ b/openfpga/src/fabric/build_top_module_memory.h @@ -34,6 +34,9 @@ void organize_top_module_memory_modules(ModuleManager& module_manager, const std::map>& cb_instance_ids, const bool& compact_routing_hierarchy); +void shuffle_top_module_configurable_children(ModuleManager& module_manager, + const ModuleId& top_module); + void add_top_module_sram_ports(ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, From 65b387a5898463f23310277d2277b3a99216aa07 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 12 Jun 2020 11:32:52 -0600 Subject: [PATCH 12/35] develop test cases for fabric keys --- .../generate_fabric_example_script.openfpga | 2 +- ...enerate_fabric_key_example_script.openfpga | 42 +++++++++++ ...rate_secure_fabric_example_script.openfpga | 74 +++++++++++++++++++ .../generate_random_key/config/task.conf | 35 +++++++++ .../generate_vanilla_key/config/task.conf | 32 ++++++++ 5 files changed, 184 insertions(+), 1 deletion(-) create mode 100644 openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga create mode 100644 openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga create mode 100644 openfpga_flow/tasks/openfpga_shell/fabric_key/generate_random_key/config/task.conf create mode 100644 openfpga_flow/tasks/openfpga_shell/fabric_key/generate_vanilla_key/config/task.conf diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga index d7f025434..38ebc9d28 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga @@ -18,7 +18,7 @@ check_netlist_naming_conflict --fix --report ./netlist_renaming.xml # Build the module graph # - Enabled compression on routing architecture modules # - Enable pin duplication on grid modules -build_fabric --compress_routing --write_fabric_key ./fabric_key.xml #--verbose +build_fabric --compress_routing #--verbose # Write the fabric hierarchy of module graph to a file # This is used by hierarchical PnR flows diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga new file mode 100644 index 000000000..d7f025434 --- /dev/null +++ b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga @@ -0,0 +1,42 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --write_fabric_key ./fabric_key.xml #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga new file mode 100644 index 000000000..4f340704b --- /dev/null +++ b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga @@ -0,0 +1,74 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing \ + --write_fabric_key ./fabric_key.xml \ + --generate_random_fabric_key + #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_random_key/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_random_key/config/task.conf new file mode 100644 index 000000000..8777a5930 --- /dev/null +++ b/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_random_key/config/task.conf @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_vanilla_key/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_vanilla_key/config/task.conf new file mode 100644 index 000000000..2893f7ba9 --- /dev/null +++ b/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_vanilla_key/config/task.conf @@ -0,0 +1,32 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From 76b82e348fb4d576424548368256ca643595d6bd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 12 Jun 2020 11:38:05 -0600 Subject: [PATCH 13/35] deploy fabric key test cases to CI --- .travis/openfpga_vpr8_reg_test.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.travis/openfpga_vpr8_reg_test.sh b/.travis/openfpga_vpr8_reg_test.sh index 046f8210f..13e9fddfb 100755 --- a/.travis/openfpga_vpr8_reg_test.sh +++ b/.travis/openfpga_vpr8_reg_test.sh @@ -102,6 +102,10 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_testbench echo -e "Testing SDC generation with time units"; python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/sdc_time_unit --debug --show_thread_logs +echo -e "Testing Secured FPGA fabrics"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_key/generate_vanilla_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_key/generate_random_key --debug --show_thread_logs + # Verify MCNC big20 benchmark suite with ModelSim # Please make sure you have ModelSim installed in the environment # Otherwise, it will fail From a5055e9d26e9b0a2f6da1e7c70260d7b11a08d76 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 12 Jun 2020 13:03:11 -0600 Subject: [PATCH 14/35] add support about loading external fabric key --- libopenfpga/libfabrickey/src/fabric_key.cpp | 4 ++ libopenfpga/libfabrickey/src/fabric_key.h | 1 + openfpga/src/base/openfpga_build_fabric.cpp | 15 +++++++ openfpga/src/fabric/build_device_module.cpp | 4 +- openfpga/src/fabric/build_device_module.h | 2 + openfpga/src/fabric/build_top_module.cpp | 22 +++++++--- openfpga/src/fabric/build_top_module.h | 2 + .../src/fabric/build_top_module_memory.cpp | 44 +++++++++++++++++++ openfpga/src/fabric/build_top_module_memory.h | 5 +++ 9 files changed, 92 insertions(+), 7 deletions(-) diff --git a/libopenfpga/libfabrickey/src/fabric_key.cpp b/libopenfpga/libfabrickey/src/fabric_key.cpp index 187150800..0c2c508bd 100644 --- a/libopenfpga/libfabrickey/src/fabric_key.cpp +++ b/libopenfpga/libfabrickey/src/fabric_key.cpp @@ -37,6 +37,10 @@ size_t FabricKey::key_value(const FabricKeyId& key_id) const { return key_values_[key_id]; } +bool FabricKey::empty() const { + return 0 == key_ids_.size(); +} + /************************************************************************ * Public Mutators ***********************************************************************/ diff --git a/libopenfpga/libfabrickey/src/fabric_key.h b/libopenfpga/libfabrickey/src/fabric_key.h index 7488923df..053e32e56 100644 --- a/libopenfpga/libfabrickey/src/fabric_key.h +++ b/libopenfpga/libfabrickey/src/fabric_key.h @@ -36,6 +36,7 @@ class FabricKey { public: /* Public Accessors: Basic data query */ std::string key_name(const FabricKeyId& key_id) const; size_t key_value(const FabricKeyId& key_id) const; + bool empty() const; public: /* Public Mutators: model-related */ void reserve_keys(const size_t& num_keys); FabricKeyId create_key(); diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp index f5c007a09..adbe8fce6 100644 --- a/openfpga/src/base/openfpga_build_fabric.cpp +++ b/openfpga/src/base/openfpga_build_fabric.cpp @@ -8,6 +8,9 @@ /* Headers from openfpgashell library */ #include "command_exit_codes.h" +/* Headers from fabrickey library */ +#include "read_xml_fabric_key.h" + #include "device_rr_gsb.h" #include "device_rr_gsb_utils.h" #include "build_device_module.h" @@ -68,6 +71,7 @@ int build_fabric(OpenfpgaContext& openfpga_ctx, CommandOptionId opt_duplicate_grid_pin = cmd.option("duplicate_grid_pin"); CommandOptionId opt_gen_random_fabric_key = cmd.option("generate_random_fabric_key"); CommandOptionId opt_write_fabric_key = cmd.option("write_fabric_key"); + CommandOptionId opt_load_fabric_key = cmd.option("load_fabric_key"); CommandOptionId opt_verbose = cmd.option("verbose"); if (true == cmd_context.option_enable(cmd, opt_compress_routing)) { @@ -78,12 +82,23 @@ int build_fabric(OpenfpgaContext& openfpga_ctx, VTR_LOG("\n"); + /* Load fabric key from file */ + FabricKey predefined_fabric_key; + if (true == cmd_context.option_enable(cmd, opt_load_fabric_key)) { + std::string fkey_fname = cmd_context.option_value(cmd, opt_load_fabric_key); + VTR_ASSERT(false == fkey_fname.empty()); + predefined_fabric_key = read_xml_fabric_key(fkey_fname.c_str()); + } + + VTR_LOG("\n"); + openfpga_ctx.mutable_module_graph() = build_device_module_graph(openfpga_ctx.mutable_io_location_map(), openfpga_ctx.mutable_decoder_lib(), const_cast(openfpga_ctx), g_vpr_ctx.device(), cmd_context.option_enable(cmd, opt_compress_routing), cmd_context.option_enable(cmd, opt_duplicate_grid_pin), + predefined_fabric_key, cmd_context.option_enable(cmd, opt_gen_random_fabric_key), cmd_context.option_enable(cmd, opt_verbose)); diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 36769636a..b988e1e29 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -32,6 +32,7 @@ ModuleManager build_device_module_graph(IoLocationMap& io_location_map, const DeviceContext& vpr_device_ctx, const bool& compress_routing, const bool& duplicate_grid_pin, + const FabricKey& fabric_key, const bool& generate_random_fabric_key, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build fabric module graph"); @@ -117,7 +118,8 @@ ModuleManager build_device_module_graph(IoLocationMap& io_location_map, openfpga_ctx.arch().arch_direct, openfpga_ctx.arch().config_protocol.type(), sram_model, - compress_routing, duplicate_grid_pin, generate_random_fabric_key); + compress_routing, duplicate_grid_pin, + fabric_key, generate_random_fabric_key); /* Now a critical correction has to be done! * In the module construction, we always use prefix of ports because they are binded diff --git a/openfpga/src/fabric/build_device_module.h b/openfpga/src/fabric/build_device_module.h index 7b8a6bd2b..34d30b997 100644 --- a/openfpga/src/fabric/build_device_module.h +++ b/openfpga/src/fabric/build_device_module.h @@ -6,6 +6,7 @@ *******************************************************************/ #include "vpr_context.h" #include "openfpga_context.h" +#include "fabric_key.h" /******************************************************************** * Function declaration @@ -20,6 +21,7 @@ ModuleManager build_device_module_graph(IoLocationMap& io_location_map, const DeviceContext& vpr_device_ctx, const bool& compress_routing, const bool& duplicate_grid_pin, + const FabricKey& fabric_key, const bool& generate_random_fabric_key, const bool& verbose); diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index a751834ef..6c2d94a00 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -322,6 +322,7 @@ void build_top_module(ModuleManager& module_manager, const CircuitModelId& sram_model, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, + const FabricKey& fabric_key, const bool& generate_random_fabric_key) { vtr::ScopedStartFinishTimer timer("Build FPGA fabric module"); @@ -363,12 +364,21 @@ void build_top_module(ModuleManager& module_manager, */ add_module_gpio_ports_from_child_modules(module_manager, top_module); - /* Organize the list of memory modules and instances */ - organize_top_module_memory_modules(module_manager, top_module, - circuit_lib, sram_orgz_type, sram_model, - grids, grid_instance_ids, - device_rr_gsb, sb_instance_ids, cb_instance_ids, - compact_routing_hierarchy); + /* Organize the list of memory modules and instances + * If we have an empty fabric key, we organize the memory modules as routine + * Otherwise, we will load the fabric key directly + */ + if (true == fabric_key.empty()) { + organize_top_module_memory_modules(module_manager, top_module, + circuit_lib, sram_orgz_type, sram_model, + grids, grid_instance_ids, + device_rr_gsb, sb_instance_ids, cb_instance_ids, + compact_routing_hierarchy); + } else { + VTR_ASSERT_SAFE(false == fabric_key.empty()); + load_top_module_memory_modules_from_fabric_key(module_manager, top_module, + fabric_key); + } /* Shuffle the configurable children in a random sequence */ if (true == generate_random_fabric_key) { diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h index fca3ea841..50bf6e611 100644 --- a/openfpga/src/fabric/build_top_module.h +++ b/openfpga/src/fabric/build_top_module.h @@ -16,6 +16,7 @@ #include "arch_direct.h" #include "module_manager.h" #include "io_location_map.h" +#include "fabric_key.h" /******************************************************************** * Function declaration @@ -37,6 +38,7 @@ void build_top_module(ModuleManager& module_manager, const CircuitModelId& sram_model, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, + const FabricKey& fabric_key, const bool& generate_random_fabric_key); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 2ac546218..158a0f44a 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -401,6 +401,50 @@ void shuffle_top_module_configurable_children(ModuleManager& module_manager, } } +/******************************************************************** + * Load configurable children from a fabric key to top-level module + * + * Note: + * - This function will overwrite any exisiting configurable children + * under the top module + * + * Return 0 - Success + * Return 1 - Fatal errors + ********************************************************************/ +int load_top_module_memory_modules_from_fabric_key(ModuleManager& module_manager, + const ModuleId& top_module, + const FabricKey& fabric_key) { + /* Ensure a clean start */ + module_manager.clear_configurable_children(top_module); + + for (const FabricKeyId& key : fabric_key.keys()) { + /* Find if the module name exist */ + ModuleId child_module = module_manager.find_module(fabric_key.key_name(key)); + if (false == module_manager.valid_module_id(child_module)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid key name '%s'!\n", + fabric_key.key_name(key).c_str()); + return 1; + } + + /* Find if instance id is valid */ + size_t child_instance = fabric_key.key_value(key); + if (child_instance >= module_manager.num_instance(top_module, child_module)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid key value '%ld'!\n", + child_instance); + return 1; + } + + /* Now we can add the child to configurable children of the top module */ + module_manager.add_configurable_child(top_module, + child_module, + child_instance); + } + + return 0; +} + /******************************************************************** * Add a list of ports that are used for SRAM configuration to the FPGA * top-level module diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h index 1c6dd56e5..c4a1ff7f6 100644 --- a/openfpga/src/fabric/build_top_module_memory.h +++ b/openfpga/src/fabric/build_top_module_memory.h @@ -14,6 +14,7 @@ #include "decoder_library.h" #include "device_grid.h" #include "device_rr_gsb.h" +#include "fabric_key.h" /******************************************************************** * Function declaration @@ -37,6 +38,10 @@ void organize_top_module_memory_modules(ModuleManager& module_manager, void shuffle_top_module_configurable_children(ModuleManager& module_manager, const ModuleId& top_module); +int load_top_module_memory_modules_from_fabric_key(ModuleManager& module_manager, + const ModuleId& top_module, + const FabricKey& fabric_key); + void add_top_module_sram_ports(ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, From 2d35848cfa80290eef657e3d205ab2510910fa85 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 12 Jun 2020 13:11:21 -0600 Subject: [PATCH 15/35] add external key test cases --- ...re_fabric_from_key_example_script.openfpga | 74 +++++++++++++++++++ .../fabric_keys/k4_N4_2x2_sample_key.xml | 36 +++++++++ .../load_external_key/config/task.conf | 36 +++++++++ 3 files changed, 146 insertions(+) create mode 100644 openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga create mode 100644 openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml create mode 100644 openfpga_flow/tasks/openfpga_shell/fabric_key/load_external_key/config/task.conf diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga new file mode 100644 index 000000000..a61336d61 --- /dev/null +++ b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga @@ -0,0 +1,74 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing \ + --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} \ + --write_fabric_key ./fabric_key.xml + #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml b/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml new file mode 100644 index 000000000..e149a311d --- /dev/null +++ b/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_key/load_external_key/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_key/load_external_key/config/task.conf new file mode 100644 index 000000000..4be35916c --- /dev/null +++ b/openfpga_flow/tasks/openfpga_shell/fabric_key/load_external_key/config/task.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= From 41585436c8a5335a6de22b7336afadf202933668 Mon Sep 17 00:00:00 2001 From: ganeshgore Date: Fri, 12 Jun 2020 15:37:12 -0600 Subject: [PATCH 16/35] Added external_fabric_key_file key --- openfpga_flow/scripts/run_fpga_flow.py | 3 +++ openfpga_flow/scripts/run_fpga_task.py | 2 ++ 2 files changed, 5 insertions(+) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index fcf47ee44..9975a506d 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -85,6 +85,8 @@ parser.add_argument('--openfpga_arch_file', type=str, help="Openfpga architecture file for shell") parser.add_argument('--openfpga_sim_setting_file', type=str, help="Openfpga simulation file for shell") +parser.add_argument('--external_fabric_key_file', type=str, + help="Key file for shell") parser.add_argument('--yosys_tmpl', type=str, help="Alternate yosys template, generates top_module.blif") parser.add_argument('--disp', action="store_true", @@ -686,6 +688,7 @@ def run_openfpga_shell(): path_variables["VPR_ARCH_FILE"] = args.arch_file path_variables["OPENFPGA_ARCH_FILE"] = args.openfpga_arch_file path_variables["OPENFPGA_SIM_SETTING_FILE"] = args.openfpga_sim_setting_file + path_variables["EXTERNAL_FABRIC_KEY_FILE"] = args.external_fabric_key_file path_variables["VPR_TESTBENCH_BLIF"] = args.top_module+".blif" path_variables["ACTIVITY_FILE"] = args.top_module+"_ace_out.act" path_variables["REFERENCE_VERILOG_TESTBENCH"] = args.top_module + \ diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 3361a3082..47492785f 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -357,6 +357,8 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf): task_gc.get("openfpga_arch_file")] command += ["--openfpga_sim_setting_file", task_gc.get("openfpga_sim_setting_file")] + command += ["--external_fabric_key_file", + task_gc.get("external_fabric_key_file")] if benchmark_obj.get("activity_file"): command += ["--activity_file", benchmark_obj.get("activity_file")] From ba38120093ce0da37505dbbf16556ddd54c7e9c9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 12 Jun 2020 16:15:16 -0600 Subject: [PATCH 17/35] add documentation for fabric key and reorganize command references --- docs/source/manual/arch_lang/fabric_key.rst | 69 +++++ docs/source/manual/arch_lang/index.rst | 2 +- docs/source/manual/openfpga_shell/index.rst | 2 +- .../openfpga_shell/openfpga_commands.rst | 280 ------------------ .../openfpga_commands/basic_commands.rst | 15 + .../fpga_bitstream_commands.rst | 31 ++ .../openfpga_commands/fpga_sdc_commands.rst | 84 ++++++ .../fpga_verilog_commands.rst | 44 +++ .../openfpga_commands/index.rst | 21 ++ .../openfpga_commands/setup_commands.rst | 127 ++++++++ .../openfpga_commands/vpr_commands.rst | 11 + 11 files changed, 404 insertions(+), 282 deletions(-) create mode 100644 docs/source/manual/arch_lang/fabric_key.rst delete mode 100644 docs/source/manual/openfpga_shell/openfpga_commands.rst create mode 100644 docs/source/manual/openfpga_shell/openfpga_commands/basic_commands.rst create mode 100644 docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst create mode 100644 docs/source/manual/openfpga_shell/openfpga_commands/fpga_sdc_commands.rst create mode 100644 docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst create mode 100644 docs/source/manual/openfpga_shell/openfpga_commands/index.rst create mode 100644 docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst create mode 100644 docs/source/manual/openfpga_shell/openfpga_commands/vpr_commands.rst diff --git a/docs/source/manual/arch_lang/fabric_key.rst b/docs/source/manual/arch_lang/fabric_key.rst new file mode 100644 index 000000000..1739551b7 --- /dev/null +++ b/docs/source/manual/arch_lang/fabric_key.rst @@ -0,0 +1,69 @@ +Fabric Key +~~~~~~~~~~ + +Fabric key is a secure key for users to generate bitstream for a specific FPGA fabric. +With this key, OpenFPGA can generate correct bitstreams for the FPGA. +Using a wrong key, OpenFPGA may error out or generate wrong bitstreams. +The fabric key support allows users to build secured/classified FPGA chips even with an open-source tool. + +.. note:: Users are the only owner of the key. OpenFPGA will not store or replicate the key. + +Key Generation +`````````````` +A fabric key can be achieved in the following ways: + +- OpenFPGA can auto-generate a fabric key using random algorithms (see detail in :ref:`cmd_build_fabric`) + +- Users can craft a fabric key based on auto-generated file by following the file format description. + +File Format +``````````` + +A fabric key follows an XML format. As shown in the following XML code, the key file includes the organization of configurable memory blocks in the top-level FPGA fabric: + + - ``id`` indicates the sequence of the configurable memory block in the top-level FPGA fabric. + + - ``name`` indicates the module name of the configurable memory block. + + - ``value`` indicates the instance id of the configurable memory block in the top-level FPGA fabric. + +The following is an example of a fabric key generate by OpenFPGA for a 2 :math:`\times` 2 FPGA. + +.. code-block:: xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/source/manual/arch_lang/index.rst b/docs/source/manual/arch_lang/index.rst index f2fd146fb..bcd6287e3 100644 --- a/docs/source/manual/arch_lang/index.rst +++ b/docs/source/manual/arch_lang/index.rst @@ -25,4 +25,4 @@ OpenFPGA Architecture Description annotate_vpr_arch - + fabric_key diff --git a/docs/source/manual/openfpga_shell/index.rst b/docs/source/manual/openfpga_shell/index.rst index 24512f67d..406fc0ddf 100644 --- a/docs/source/manual/openfpga_shell/index.rst +++ b/docs/source/manual/openfpga_shell/index.rst @@ -11,4 +11,4 @@ OpenFPGA Shell openfpga_script - openfpga_commands + openfpga_commands/index diff --git a/docs/source/manual/openfpga_shell/openfpga_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands.rst deleted file mode 100644 index eb5929861..000000000 --- a/docs/source/manual/openfpga_shell/openfpga_commands.rst +++ /dev/null @@ -1,280 +0,0 @@ -.. _openfpga_commands: - -Commands --------- - -As OpenFPGA integrates various tools, the commands are categorized into different classes: - -Basic Commands -~~~~~~~~~~~~~~ - -.. option:: help - - Show help desk to list all the available commands - -.. option:: exit - - Exit OpenFPGA shell - -VPR -~~~ - -.. option:: vpr - - OpenFPGA allows users to call ``vpr`` in the standard way as documented in vtr project. - -Setup OpenFPGA -~~~~~~~~~~~~~~ - -.. option:: read_openfpga_arch - - Read the XML file about architecture description (see details in :ref:`arch_generality`) - - - ``--file`` or ``-f`` Specify the file name - - - ``--verbose`` Show verbose log - -.. option:: write_openfpga_arch - - Write the OpenFPGA XML architecture file to a file - - - ``--file`` or ``-f`` Specify the file name - - - ``--verbose`` Show verbose log - -.. option:: read_openfpga_simulation_setting - - Read the XML file about simulation settings (see details in :ref:`simulation_setting`) - - - ``--file`` or ``-f`` Specify the file name - - - ``--verbose`` Show verbose log - -.. option:: write_openfpga_simulation_setting - - Write the OpenFPGA XML simulation settings to a file - - - ``--file`` or ``-f`` Specify the file name - - - ``--verbose`` Show verbose log - -.. option:: link_openfpga_arch - - Annotate the OpenFPGA architecture to VPR data base - - - ``--activity_file`` Specify the signal activity file - - - ``--sort_gsb_chan_node_in_edges`` Sort the edges for the routing tracks in General Switch Blocks (GSBs). Strongly recommand to turn this on for uniquifying the routing modules - - - ``--verbose`` Show verbose log - -.. option:: write_gsb_to_xml - - Write the internal structure of General Switch Blocks (GSBs) across a FPGA fabric, including the interconnection between the nodes and node-level details, to XML files - - - ``--file`` or ``-f`` Specify the output directory of the XML files. Each GSB will be written to an indepedent XML file - - - ``--verbose`` Show verbose log - - .. note:: This command is used to help users to study the difference between GSBs - -.. option:: check_netlist_naming_conflict - - Check and correct any naming conflicts in the BLIF netlist - This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully. - - .. warning:: This command may be deprecated in future when it is merged to VPR upstream - - - ``--fix`` Apply fix-up to the names that violate the syntax - - - ``--report <.xml>`` Report the naming fix-up to a log file - -.. option:: pb_pin_fixup - - Apply fix-up to clustering nets based on routing results - This is strongly recommended. Otherwise, the bitstream generation may be wrong - - .. warning:: This command may be deprecated in future when it is merged to VPR upstream - - - ``--verbose`` Show verbose log - -.. option:: lut_truth_table_fixup - - Apply fix-up to Look-Up Table truth tables based on packing results - - .. warning:: This command may be deprecated in future when it is merged to VPR upstream - - - ``--verbose`` Show verbose log - -.. option:: build_fabric - - Build the module graph. - - - ``--compress_routing`` Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly. - - - ``--duplicate_grid_pin`` Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed - - - ``--verbose`` Show verbose log - - .. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE - -.. option:: write_fabric_hierarchy - - Write the hierarchy of FPGA fabric graph to a plain-text file - - - ``--file`` or ``-f`` Specify the file name to write the hierarchy. - - - ``--depth`` Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1. - - - ``--verbose`` Show verbose log - - .. note:: This file is designed for hierarchical PnR flow, which requires the tree of Multiple-Instanced-Blocks (MIBs). - -FPGA-Bitstream -~~~~~~~~~~~~~~ - -.. option:: repack - - Repack the netlist to physical pbs - This must be done before bitstream generator and testbench generation - Strongly recommend it is done after all the fix-up have been applied - - - ``--verbose`` Show verbose log - -.. option:: build_architecture_bitstream - - Decode VPR implementing results to an fabric-independent bitstream database - - - ``--file`` or ``-f`` Output the fabric-independent bitstream to an XML file - - - ``--verbose`` Show verbose log - -.. option:: build_fabric_bitstream - - Build a sequence for every configuration bits in the bitstream database for a specific FPGA fabric - - - ``--file`` or ``-f`` Output the fabric bitstream to an plain text file (only 0 or 1) - - - ``--verbose`` Show verbose log - -.. _openfpga_verilog_commands: - -FPGA-Verilog -~~~~~~~~~~~~ - -.. option:: write_fabric_verilog - - Write the Verilog netlist for FPGA fabric based on module graph - - - ``--file`` or ``-f`` Specify the output directory for the Verilog netlists - - - ``--explicit_port_mapping`` Use explicit port mapping when writing the Verilog netlists - - - ``--include_timing`` Output timing information to Verilog netlists for primitive modules - - - ``--include_signal_init`` Output signal initialization to Verilog netlists for primitive modules - - - ``--support_icarus_simulator`` Output Verilog netlists with syntax that iVerilog simulatorcan accept - - - ``--print_user_defined_template`` Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists - - - ``--verbose`` Show verbose log - -.. option:: write_verilog_testbench - - Write the Verilog testbench for FPGA fabric - - - ``--file`` or ``-f`` The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists - - - ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches - - - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to memory bank and frame-based configuration protocols. When enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. - - - ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA - - - ``--print_formal_verification_top_netlist`` Generate a top-level module which can be used in formal verification - - - ``--print_preconfig_top_testbench`` Enable pre-configured top-level testbench which is a fast verification skipping programming phase - - - ``--print_simulation_ini`` Output an exchangeable simulation ini file, which is needed only when you need to interface different HDL simulators using openfpga flow-run scripts - - - ``--explicit_port_mapping`` Use explicit port mapping when writing the Verilog netlists - -FPGA-SDC -~~~~~~~~ - -.. option:: write_pnr_sdc - - Write the SDC files for PnR backend - - - ``--file`` or ``-f`` Specify the output directory for SDC files - - - ``--hierarchical`` Output SDC files without full path in hierarchy - - - ``--flatten_names`` Use flatten names (no wildcards) in SDC files - - - ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``). - - - ``--output_hierarchy`` Output hierarchy of Multiple-Instance-Blocks(MIBs) to plain text file. This is applied to constrain timing for grids, Switch Blocks and Connection Blocks. - - .. note:: Valid only when ``compress_routing`` is enabled in ``build_fabric`` - - - ``--constrain_global_port`` Constrain all the global ports of FPGA fabric. - - - ``--constrain_non_clock_global_port`` Constrain all the non-clock global ports as clocks ports of FPGA fabric - - .. note:: ``constrain_global_port`` will treat these global ports in Clock Tree Synthesis (CTS), in purpose of balancing the delay to each sink. Be carefull to enable ``constrain_non_clock_global_port``, this may significanly increase the runtime of CTS as it is supposed to be routed before any other nets. This may cause routing congestion as well. - - - ``--constrain_grid`` Constrain all the grids of FPGA fabric - - - ``--constrain_sb`` Constrain all the switch blocks of FPGA fabric - - - ``--constrain_cb`` Constrain all the connection blocks of FPGA fabric - - - ``--constrain_configurable_memory_outputs`` Constrain all the outputs of configurable memories of FPGA fabric - - - ``--constrain_routing_multiplexer_outputs`` Constrain all the outputs of routing multiplexer of FPGA fabric - - - ``--constrain_switch_block_outputs`` Constrain all the outputs of switch blocks of FPGA fabric - - - ``--constrain_zero_delay_paths`` Constrain all the zero-delay paths in FPGA fabric - - .. note:: Zero-delay path may cause errors in some PnR tools as it is considered illegal - - - ``--verbose`` Enable verbose output - -.. option:: write_configuration_chain_sdc - - Write the SDC file to constrain the timing for configuration chain. The timing constraints will always start from the first output (Q) of a Configuration Chain Flip-flop (CCFF) and ends at the inputs of the next CCFF in the chain. Note that Qb of CCFF will not be constrained! - - - ``--file`` or ``-f`` Specify the output SDC file - - - ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``). - - - - ``--max_delay`` Specify the maximum delay to be used. The timing value should follow the time unit defined in this command. - - - ``--min_delay`` Specify the minimum delay to be used. The timing value should follow the time unit defined in this command. - - .. note:: - Only applicable when configuration chain is used as configuration protocol - -.. option:: write_sdc_disable_timing_configure_ports - - Write the SDC file to disable timing for configure ports of programmable modules. The SDC aims to break the combinational loops across FPGAs and avoid false path timing to be visible to timing analyzers - - - ``--file`` or ``-f`` Specify the output SDC file - - - ``--flatten_names`` Use flatten names (no wildcards) in SDC files - - - ``--verbose`` Show verbose log - -.. option:: write_analysis_sdc - - Write the SDC to run timing analysis for a mapped FPGA fabric - - - ``--file`` or ``-f`` Specify the output directory for SDC files - - - ``--flatten_names`` Use flatten names (no wildcards) in SDC files - - - ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``). diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/basic_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/basic_commands.rst new file mode 100644 index 000000000..727448a61 --- /dev/null +++ b/docs/source/manual/openfpga_shell/openfpga_commands/basic_commands.rst @@ -0,0 +1,15 @@ +.. _openfpga_basic_commands: + +Basic Commands +-------------- + +help +~~~~ + + Show help desk to list all the available commands + +exit +~~~~ + + Exit OpenFPGA shell + diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst new file mode 100644 index 000000000..62ab8bec4 --- /dev/null +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst @@ -0,0 +1,31 @@ +.. _openfpga_bitstream_commands: + +FPGA-Bitstream +-------------- + +repack +~~~~~~ + + Repack the netlist to physical pbs + This must be done before bitstream generator and testbench generation + Strongly recommend it is done after all the fix-up have been applied + + - ``--verbose`` Show verbose log + +build_architecture_bitstream +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Decode VPR implementing results to an fabric-independent bitstream database + + - ``--file`` or ``-f`` Output the fabric-independent bitstream to an XML file + + - ``--verbose`` Show verbose log + +build_fabric_bitstream +~~~~~~~~~~~~~~~~~~~~~~ + + Build a sequence for every configuration bits in the bitstream database for a specific FPGA fabric + + - ``--file`` or ``-f`` Output the fabric bitstream to an plain text file (only 0 or 1) + + - ``--verbose`` Show verbose log diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_sdc_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_sdc_commands.rst new file mode 100644 index 000000000..f5f0b83af --- /dev/null +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_sdc_commands.rst @@ -0,0 +1,84 @@ +.. _openfpga_sdc_commands: + +FPGA-SDC +-------- + +write_pnr_sdc +~~~~~~~~~~~~~ + + Write the SDC files for PnR backend + + - ``--file`` or ``-f`` Specify the output directory for SDC files + + - ``--hierarchical`` Output SDC files without full path in hierarchy + + - ``--flatten_names`` Use flatten names (no wildcards) in SDC files + + - ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``). + + - ``--output_hierarchy`` Output hierarchy of Multiple-Instance-Blocks(MIBs) to plain text file. This is applied to constrain timing for grids, Switch Blocks and Connection Blocks. + + .. note:: Valid only when ``compress_routing`` is enabled in ``build_fabric`` + + - ``--constrain_global_port`` Constrain all the global ports of FPGA fabric. + + - ``--constrain_non_clock_global_port`` Constrain all the non-clock global ports as clocks ports of FPGA fabric + + .. note:: ``constrain_global_port`` will treat these global ports in Clock Tree Synthesis (CTS), in purpose of balancing the delay to each sink. Be carefull to enable ``constrain_non_clock_global_port``, this may significanly increase the runtime of CTS as it is supposed to be routed before any other nets. This may cause routing congestion as well. + + - ``--constrain_grid`` Constrain all the grids of FPGA fabric + + - ``--constrain_sb`` Constrain all the switch blocks of FPGA fabric + + - ``--constrain_cb`` Constrain all the connection blocks of FPGA fabric + + - ``--constrain_configurable_memory_outputs`` Constrain all the outputs of configurable memories of FPGA fabric + + - ``--constrain_routing_multiplexer_outputs`` Constrain all the outputs of routing multiplexer of FPGA fabric + + - ``--constrain_switch_block_outputs`` Constrain all the outputs of switch blocks of FPGA fabric + + - ``--constrain_zero_delay_paths`` Constrain all the zero-delay paths in FPGA fabric + + .. note:: Zero-delay path may cause errors in some PnR tools as it is considered illegal + + - ``--verbose`` Enable verbose output + +write_configuration_chain_sdc +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Write the SDC file to constrain the timing for configuration chain. The timing constraints will always start from the first output (Q) of a Configuration Chain Flip-flop (CCFF) and ends at the inputs of the next CCFF in the chain. Note that Qb of CCFF will not be constrained! + + - ``--file`` or ``-f`` Specify the output SDC file + + - ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``). + + + - ``--max_delay`` Specify the maximum delay to be used. The timing value should follow the time unit defined in this command. + + - ``--min_delay`` Specify the minimum delay to be used. The timing value should follow the time unit defined in this command. + + .. note:: + Only applicable when configuration chain is used as configuration protocol + +write_sdc_disable_timing_configure_ports +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Write the SDC file to disable timing for configure ports of programmable modules. The SDC aims to break the combinational loops across FPGAs and avoid false path timing to be visible to timing analyzers + + - ``--file`` or ``-f`` Specify the output SDC file + + - ``--flatten_names`` Use flatten names (no wildcards) in SDC files + + - ``--verbose`` Show verbose log + +write_analysis_sdc +~~~~~~~~~~~~~~~~~~ + + Write the SDC to run timing analysis for a mapped FPGA fabric + + - ``--file`` or ``-f`` Specify the output directory for SDC files + + - ``--flatten_names`` Use flatten names (no wildcards) in SDC files + + - ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``). diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst new file mode 100644 index 000000000..de4aecad8 --- /dev/null +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -0,0 +1,44 @@ +.. _openfpga_verilog_commands: + +FPGA-Verilog +------------ + +write_fabric_verilog +~~~~~~~~~~~~~~~~~~~~ + + Write the Verilog netlist for FPGA fabric based on module graph + + - ``--file`` or ``-f`` Specify the output directory for the Verilog netlists + + - ``--explicit_port_mapping`` Use explicit port mapping when writing the Verilog netlists + + - ``--include_timing`` Output timing information to Verilog netlists for primitive modules + + - ``--include_signal_init`` Output signal initialization to Verilog netlists for primitive modules + + - ``--support_icarus_simulator`` Output Verilog netlists with syntax that iVerilog simulatorcan accept + + - ``--print_user_defined_template`` Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists + + - ``--verbose`` Show verbose log + +write_verilog_testbench +~~~~~~~~~~~~~~~~~~~~~~~ + + Write the Verilog testbench for FPGA fabric + + - ``--file`` or ``-f`` The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists + + - ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches + + - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to memory bank and frame-based configuration protocols. When enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. + + - ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA + + - ``--print_formal_verification_top_netlist`` Generate a top-level module which can be used in formal verification + + - ``--print_preconfig_top_testbench`` Enable pre-configured top-level testbench which is a fast verification skipping programming phase + + - ``--print_simulation_ini`` Output an exchangeable simulation ini file, which is needed only when you need to interface different HDL simulators using openfpga flow-run scripts + + - ``--explicit_port_mapping`` Use explicit port mapping when writing the Verilog netlists diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/index.rst b/docs/source/manual/openfpga_shell/openfpga_commands/index.rst new file mode 100644 index 000000000..2a9f871b6 --- /dev/null +++ b/docs/source/manual/openfpga_shell/openfpga_commands/index.rst @@ -0,0 +1,21 @@ +Commands +-------- + +As OpenFPGA integrates various tools, the commands are categorized into different classes: + +.. _openfpga_commands: + +.. toctree:: + :maxdepth: 2 + + basic_commands + + vpr_commands + + setup_commands + + fpga_bitstream_commands + + fpga_verilog_commands + + fpga_sdc_commands diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst new file mode 100644 index 000000000..aa0018476 --- /dev/null +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -0,0 +1,127 @@ +.. _openfpga_setup_commands: + +Setup OpenFPGA +-------------- + +read_openfpga_arch +~~~~~~~~~~~~~~~~~~ + + Read the XML file about architecture description (see details in :ref:`arch_generality`) + + - ``--file`` or ``-f`` Specify the file name + + - ``--verbose`` Show verbose log + +write_openfpga_arch +~~~~~~~~~~~~~~~~~~~ + + Write the OpenFPGA XML architecture file to a file + + - ``--file`` or ``-f`` Specify the file name + + - ``--verbose`` Show verbose log + +read_openfpga_simulation_setting +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Read the XML file about simulation settings (see details in :ref:`simulation_setting`) + + - ``--file`` or ``-f`` Specify the file name + + - ``--verbose`` Show verbose log + +write_openfpga_simulation_setting +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Write the OpenFPGA XML simulation settings to a file + + - ``--file`` or ``-f`` Specify the file name + + - ``--verbose`` Show verbose log + +link_openfpga_arch +~~~~~~~~~~~~~~~~~~ + + Annotate the OpenFPGA architecture to VPR data base + + - ``--activity_file`` Specify the signal activity file + + - ``--sort_gsb_chan_node_in_edges`` Sort the edges for the routing tracks in General Switch Blocks (GSBs). Strongly recommand to turn this on for uniquifying the routing modules + + - ``--verbose`` Show verbose log + +write_gsb_to_xml +~~~~~~~~~~~~~~~~ + + Write the internal structure of General Switch Blocks (GSBs) across a FPGA fabric, including the interconnection between the nodes and node-level details, to XML files + + - ``--file`` or ``-f`` Specify the output directory of the XML files. Each GSB will be written to an indepedent XML file + + - ``--verbose`` Show verbose log + + .. note:: This command is used to help users to study the difference between GSBs + +check_netlist_naming_conflict +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Check and correct any naming conflicts in the BLIF netlist + This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully. + + .. warning:: This command may be deprecated in future when it is merged to VPR upstream + + - ``--fix`` Apply fix-up to the names that violate the syntax + + - ``--report <.xml>`` Report the naming fix-up to a log file + +pb_pin_fixup +~~~~~~~~~~~~ + + Apply fix-up to clustering nets based on routing results + This is strongly recommended. Otherwise, the bitstream generation may be wrong + + .. warning:: This command may be deprecated in future when it is merged to VPR upstream + + - ``--verbose`` Show verbose log + +lut_truth_table_fixup +~~~~~~~~~~~~~~~~~~~~~ + + Apply fix-up to Look-Up Table truth tables based on packing results + + .. warning:: This command may be deprecated in future when it is merged to VPR upstream + + - ``--verbose`` Show verbose log + +.. _cmd_build_fabric: + +build_fabric +~~~~~~~~~~~~ + + Build the module graph. + + - ``--compress_routing`` Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly. + + - ``--duplicate_grid_pin`` Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed + + - ``--load_fabric_key `` Load an external fabric key from an XML file. + + - ``--generate_fabric_key`` Generate a fabric key in a random way + + - ``--write_fabric_key `` Output current fabric key to an XML file + + - ``--verbose`` Show verbose log + + .. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE + +write_fabric_hierarchy +~~~~~~~~~~~~~~~~~~~~~~ + + Write the hierarchy of FPGA fabric graph to a plain-text file + + - ``--file`` or ``-f`` Specify the file name to write the hierarchy. + + - ``--depth`` Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1. + + - ``--verbose`` Show verbose log + + .. note:: This file is designed for hierarchical PnR flow, which requires the tree of Multiple-Instanced-Blocks (MIBs). diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/vpr_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/vpr_commands.rst new file mode 100644 index 000000000..cbdad4a53 --- /dev/null +++ b/docs/source/manual/openfpga_shell/openfpga_commands/vpr_commands.rst @@ -0,0 +1,11 @@ +.. _openfpga_vpr_commands: + +VPR Commands +------------ + +vpr +~~~ + + OpenFPGA allows users to call ``vpr`` in the standard way as documented in the vtr_project_. + +.. _vtr_project: https://github.com/verilog-to-routing/vtr-verilog-to-routing From 0d81f60fd8712fe032d69c7b921b8e972e9fd23d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 12 Jun 2020 19:48:39 -0600 Subject: [PATCH 18/35] add new options to openfpga task configuration files --- .../tasks/openfpga_shell/behavioral_verilog/config/task.conf | 1 + .../tasks/openfpga_shell/bram/dpram16k/config/task.conf | 1 + .../tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf | 1 + .../tasks/openfpga_shell/duplicated_grid_pin/config/task.conf | 1 + .../openfpga_shell/fabric_chain/adder_chain/config/task.conf | 1 + .../openfpga_shell/fabric_chain/register_chain/config/task.conf | 1 + .../openfpga_shell/fabric_chain/scan_chain/config/task.conf | 1 + .../fabric_key/generate_random_key/config/task.conf | 1 + .../fabric_key/generate_vanilla_key/config/task.conf | 1 + .../openfpga_shell/fixed_simulation_settings/config/task.conf | 1 + .../tasks/openfpga_shell/flatten_routing/config/task.conf | 1 + .../full_testbench/configuration_chain/config/task.conf | 1 + .../full_testbench/configuration_frame/config/task.conf | 1 + .../full_testbench/fast_configuration_frame/config/task.conf | 1 + .../full_testbench/fast_memory_bank/config/task.conf | 1 + .../full_testbench/flatten_memory/config/task.conf | 1 + .../openfpga_shell/full_testbench/memory_bank/config/task.conf | 1 + .../tasks/openfpga_shell/generate_fabric/config/task.conf | 1 + .../tasks/openfpga_shell/generate_testbench/config/task.conf | 1 + openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf | 1 + .../tasks/openfpga_shell/implicit_verilog/config/task.conf | 1 + openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf | 1 + .../tasks/openfpga_shell/io/multi_io_capacity/config/task.conf | 1 + .../tasks/openfpga_shell/io/reduced_io/config/task.conf | 1 + .../tasks/openfpga_shell/lut_design/frac_lut/config/task.conf | 1 + .../lut_design/intermediate_buffer/config/task.conf | 1 + .../tasks/openfpga_shell/lut_design/single_mode/config/task.conf | 1 + openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf | 1 + .../openfpga_shell/mux_design/local_encoder/config/task.conf | 1 + .../openfpga_shell/mux_design/stdcell_mux2/config/task.conf | 1 + .../openfpga_shell/mux_design/tree_structure/config/task.conf | 1 + .../preconfig_testbench/configuration_chain/config/task.conf | 1 + .../preconfig_testbench/configuration_frame/config/task.conf | 1 + .../preconfig_testbench/flatten_memory/config/task.conf | 1 + .../preconfig_testbench/memory_bank/config/task.conf | 1 + .../tasks/openfpga_shell/sdc_time_unit/config/task.conf | 1 + openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf | 1 + openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf | 1 + 38 files changed, 38 insertions(+) diff --git a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf index 3693bd3db..2a904e42e 100644 --- a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf index 93e491745..266de6a39 100644 --- a/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf index 3d89335d9..0c681a8ba 100644 --- a/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf index 328203c08..bc644f527 100644 --- a/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf index 4ab0447a3..4c7e8c562 100644 --- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf index 06441b7f3..721e4fe4b 100644 --- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf index 0d1f49c94..893510c6b 100644 --- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_random_key/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_random_key/config/task.conf index 8777a5930..e32ed3691 100644 --- a/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_random_key/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_random_key/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_vanilla_key/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_vanilla_key/config/task.conf index 2893f7ba9..3878b0a66 100644 --- a/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_vanilla_key/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/fabric_key/generate_vanilla_key/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf index 813aabc03..10904ffad 100644 --- a/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf index 36bdb28bd..351ba7d15 100644 --- a/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/config/task.conf index 9b4921136..8aa859ce2 100644 --- a/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf index e99b9c2ab..c1510b55e 100644 --- a/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf index 0a95022d3..26f9532ba 100644 --- a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf index eb3aafbd3..a07b68254 100644 --- a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf index b893a163f..9fe9eea6e 100644 --- a/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf index fadc53968..508935fa0 100644 --- a/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf b/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf index 077bafbc5..edfe6181f 100644 --- a/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf b/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf index 02d4fb597..0892e9364 100644 --- a/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf index 2d8c162d0..899fc9aab 100644 --- a/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf index 36cc8208d..00447677c 100644 --- a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf index ab8b7849e..27f428808 100644 --- a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= ##################################### # Debugging status diff --git a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf index c751ed64c..18316d71d 100644 --- a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf index 17b2c8564..92e2d8403 100644 --- a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf index 39bbeb784..e19f2d087 100644 --- a/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf index 885569b51..8529ef721 100644 --- a/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf index 0c735e07f..514ccfa09 100644 --- a/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf index e839812a6..45f359d7d 100644 --- a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf index 7b48cf6e2..de42dcc89 100644 --- a/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf index 08bebdf04..c338543fc 100644 --- a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf index 48633266c..b115aa4b3 100644 --- a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf index 9c9fc9627..257b77576 100644 --- a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf index e55a6ea8e..e2c4749fe 100644 --- a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf index 78d1e818c..8ef21c6ae 100644 --- a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf index c9505c1d5..367521841 100644 --- a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf b/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf index 11cd98766..4e3886f9e 100644 --- a/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf index d7d55eb62..dd50eacd8 100644 --- a/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf index a7e1939ed..52d05da7b 100644 --- a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf @@ -17,6 +17,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml From e1a1627899fb1b1b12e30df260640e0f8af7806f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 12 Jun 2020 21:41:21 -0600 Subject: [PATCH 19/35] deploy load external key test case to CI --- .travis/openfpga_vpr8_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis/openfpga_vpr8_reg_test.sh b/.travis/openfpga_vpr8_reg_test.sh index 13e9fddfb..8c07480cd 100755 --- a/.travis/openfpga_vpr8_reg_test.sh +++ b/.travis/openfpga_vpr8_reg_test.sh @@ -105,6 +105,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/sdc_time_unit --de echo -e "Testing Secured FPGA fabrics"; python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_key/generate_vanilla_key --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_key/generate_random_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_key/load_external_key --debug --show_thread_logs # Verify MCNC big20 benchmark suite with ModelSim # Please make sure you have ModelSim installed in the environment From 3d56cd306050adb03f9480ce7d1c3c86ff8dd1ac Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 15 Jun 2020 20:09:46 -0600 Subject: [PATCH 20/35] fine tuning on the script for MCNC benchmarks --- openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga index dc7af60ae..5f17a5c65 100644 --- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga @@ -48,7 +48,7 @@ write_fabric_verilog --file ./SRC \ --explicit_port_mapping \ --include_timing \ --include_signal_init - #--support_icarus_simulator +# --support_icarus_simulator # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists From 9d0e002532f5ea6547ecbd321b7a2d649ef175ec Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Jun 2020 21:29:45 -0600 Subject: [PATCH 21/35] echo path in architecture bitstream database --- .../fpga_bitstream/arch_bitstream_writer.cpp | 7 ++++++- .../src/fpga_bitstream/bitstream_manager.cpp | 20 +++++++++++++++++++ .../src/fpga_bitstream/bitstream_manager.h | 9 +++++++++ .../fpga_bitstream/build_grid_bitstream.cpp | 2 ++ .../build_routing_bitstream.cpp | 4 ++++ 5 files changed, 41 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp b/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp index 7f7e8ed07..eeaa5a417 100644 --- a/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp +++ b/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp @@ -82,7 +82,12 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp, /* Output child bits under this block */ size_t bit_counter = 0; - fp << "\t" << std::endl; + fp << "\t" << std::endl; for (const ConfigBitId& child_bit : bitstream_manager.block_bits(block)) { fp << "\t\t& shared_config_bits) { /* Ensure the input ids are valid */ VTR_ASSERT(true == valid_bit_id(bit)); @@ -184,4 +200,8 @@ bool BitstreamManager::valid_block_id(const ConfigBlockId& block_id) const { return (size_t(block_id) < block_ids_.size()) && (block_id == block_ids_[block_id]); } +bool BitstreamManager::valid_block_path_id(const ConfigBlockId& block_id) const { + return (true == valid_block_id(block_id)) && (-2 != block_path_id(block_id)); +} + } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/bitstream_manager.h b/openfpga/src/fpga_bitstream/bitstream_manager.h index 58a2af8ee..4ed2570bd 100644 --- a/openfpga/src/fpga_bitstream/bitstream_manager.h +++ b/openfpga/src/fpga_bitstream/bitstream_manager.h @@ -82,6 +82,9 @@ class BitstreamManager { /* Find the child block in a bitstream manager with a given name */ ConfigBlockId find_child_block(const ConfigBlockId& block_id, const std::string& child_block_name) const; + /* Find path id of a block */ + int block_path_id(const ConfigBlockId& block_id) const; + public: /* Public Mutators */ /* Add a new configuration bit to the bitstream manager */ ConfigBitId add_bit(const bool& bit_value); @@ -95,6 +98,9 @@ class BitstreamManager { /* Add a configuration bit to a block */ void add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit); + /* Add a path id to a block */ + void add_path_id_to_block(const ConfigBlockId& block, const int& path_id); + /* Add share configuration bits to a configuration bit */ void add_shared_config_bit_values(const ConfigBitId& bit, const std::vector& shared_config_bits); @@ -103,6 +109,8 @@ class BitstreamManager { bool valid_block_id(const ConfigBlockId& block_id) const; + bool valid_block_path_id(const ConfigBlockId& block_id) const; + private: /* Internal data */ /* Unique id of a block of bits in the Bitstream */ vtr::vector block_ids_; @@ -118,6 +126,7 @@ class BitstreamManager { vtr::vector block_names_; vtr::vector parent_block_ids_; vtr::vector> child_block_ids_; + vtr::vector block_path_ids_; /* Unique id of a bit in the Bitstream */ vtr::vector bit_ids_; diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index 204d7b31e..20a8ccf0a 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -203,6 +203,8 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag /* Link the memory bits to the mux mem block */ bitstream_manager.add_bit_to_block(mux_mem_block, config_bit); } + /* Record path ids */ + bitstream_manager.add_path_id_to_block(mux_mem_block, mux_input_pin_id); break; } default: diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp index 0713fcb09..6f0803c03 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp @@ -85,6 +85,8 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager, /* Link the memory bits to the mux mem block */ bitstream_manager.add_bit_to_block(mux_mem_block, config_bit); } + /* Record path ids */ + bitstream_manager.add_path_id_to_block(mux_mem_block, path_id); } /******************************************************************** @@ -239,6 +241,8 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager, /* Link the memory bits to the mux mem block */ bitstream_manager.add_bit_to_block(mux_mem_block, config_bit); } + /* Record path ids */ + bitstream_manager.add_path_id_to_block(mux_mem_block, path_id); } From 19c0b57df6897462077a0976c2b9f2ed9f356395 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Jun 2020 22:26:36 -0600 Subject: [PATCH 22/35] ignore invalid nets when decoding bitstream --- .../fpga_bitstream/build_grid_bitstream.cpp | 4 ++ .../build_routing_bitstream.cpp | 37 +++++++++++++------ 2 files changed, 29 insertions(+), 12 deletions(-) diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index 20a8ccf0a..2d31fb2bc 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -159,11 +159,15 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag /* Find the path id: * - if des pb is not valid, this is an unmapped pb, we can set a default path_id + * - There is no net mapped to des_pb_graph_pin we use default path id + * - There is a net mapped to des_pin_graph_pin: we find the path id */ const PhysicalPbId& des_pb_id = physical_pb.find_pb(des_pb_graph_pin->parent_node); size_t mux_input_pin_id = 0; if (true != physical_pb.valid_pb_id(des_pb_id)) { mux_input_pin_id = DEFAULT_PATH_ID; + } else if (AtomNetId::INVALID() == physical_pb.pb_graph_pin_atom_net(des_pb_id, des_pb_graph_pin)) { + mux_input_pin_id = DEFAULT_PATH_ID; } else { for (t_pb_graph_pin* src_pb_graph_pin : pb_graph_pin_inputs(des_pb_graph_pin, cur_interc)) { const PhysicalPbId& src_pb_id = physical_pb.find_pb(src_pb_graph_pin->parent_node); diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp index 6f0803c03..5b5e38c7d 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp @@ -50,12 +50,18 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager, /* Find the input size of the implementation of a routing multiplexer */ size_t datapath_mux_size = drive_rr_nodes.size(); - /* Find out which routing path is used in this MUX */ + /* Find out which routing path is used in this MUX + * Two conditions to be considered: + * - There is no net mapped to cur_rr_node: we use default path id + * - There is a net mapped to cur_rr_node: we find the path id + */ int path_id = DEFAULT_PATH_ID; - for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) { - if (routing_annotation.rr_node_net(drive_rr_nodes[inode]) == routing_annotation.rr_node_net(cur_rr_node)) { - path_id = (int)inode; - break; + if (ClusterNetId::INVALID() != routing_annotation.rr_node_net(cur_rr_node)) { + for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) { + if (routing_annotation.rr_node_net(drive_rr_nodes[inode]) == routing_annotation.rr_node_net(cur_rr_node)) { + path_id = (int)inode; + break; + } } } @@ -205,13 +211,21 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager, /* Configuration bits for MUX*/ int path_id = DEFAULT_PATH_ID; int edge_index = 0; - for (const RREdgeId& edge : rr_graph.node_in_edges(src_rr_node)) { - RRNodeId driver_node = rr_graph.edge_src_node(edge); - if (routing_annotation.rr_node_net(driver_node) == routing_annotation.rr_node_net(src_rr_node)) { - path_id = edge_index; - break; + + /* Find which path is connected to the output of this routing multiplexer + * Two conditions to be considered: + * - There is no net mapped to src_rr_node: we use default path id + * - There is a net mapped to src_rr_node: we find the path id + */ + if (ClusterNetId::INVALID() != routing_annotation.rr_node_net(src_rr_node)) { + for (const RREdgeId& edge : rr_graph.node_in_edges(src_rr_node)) { + RRNodeId driver_node = rr_graph.edge_src_node(edge); + if (routing_annotation.rr_node_net(driver_node) == routing_annotation.rr_node_net(src_rr_node)) { + path_id = edge_index; + break; + } + edge_index++; } - edge_index++; } /* Ensure that our path id makes sense! */ @@ -219,7 +233,6 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager, || ( (DEFAULT_PATH_ID < path_id) && (path_id < (int)datapath_mux_size) ) ); - /* Find the circuit model id of the mux, we need its design technology which matters the bitstream generation */ std::vector driver_switches = get_rr_graph_driver_switches(rr_graph, src_rr_node); VTR_ASSERT(1 == driver_switches.size()); From b91c30191a88de6b1a1ad3be644c4b21486f44ea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jun 2020 00:04:55 -0600 Subject: [PATCH 23/35] add input and output net echo in arch bitstream database --- openfpga/src/base/openfpga_bitstream.cpp | 1 + .../fpga_bitstream/arch_bitstream_writer.cpp | 38 ++++++++++- .../fpga_bitstream/arch_bitstream_writer.h | 2 + .../src/fpga_bitstream/bitstream_manager.cpp | 34 ++++++++++ .../src/fpga_bitstream/bitstream_manager.h | 36 +++++++++++ .../fpga_bitstream/build_device_bitstream.cpp | 1 + .../fpga_bitstream/build_grid_bitstream.cpp | 22 ++++++- .../build_routing_bitstream.cpp | 64 +++++++++++++++---- .../fpga_bitstream/build_routing_bitstream.h | 1 + 9 files changed, 180 insertions(+), 19 deletions(-) diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp index b1af639b5..1a6345040 100644 --- a/openfpga/src/base/openfpga_bitstream.cpp +++ b/openfpga/src/base/openfpga_bitstream.cpp @@ -43,6 +43,7 @@ int fpga_bitstream(OpenfpgaContext& openfpga_ctx, create_directory(src_dir_path); write_arch_independent_bitstream_to_xml_file(openfpga_ctx.bitstream_manager(), + g_vpr_ctx.atom(), cmd_context.option_value(cmd, opt_file)); } diff --git a/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp b/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp index eeaa5a417..3006a6db6 100644 --- a/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp +++ b/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp @@ -51,13 +51,14 @@ void write_bitstream_xml_file_head(std::fstream& fp) { *******************************************************************/ static void rec_write_block_bitstream_to_xml_file(std::fstream& fp, + const AtomContext& atom_ctx, const BitstreamManager& bitstream_manager, const ConfigBlockId& block) { valid_file_stream(fp); /* Dive to child blocks if this block has any */ for (const ConfigBlockId& child_block : bitstream_manager.block_children(block)) { - rec_write_block_bitstream_to_xml_file(fp, bitstream_manager, child_block); + rec_write_block_bitstream_to_xml_file(fp, atom_ctx, bitstream_manager, child_block); } if (0 == bitstream_manager.block_bits(block).size()) { @@ -80,6 +81,37 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp, } fp << "\t" << std::endl; + /* Output input/output nets if there are any */ + if (false == bitstream_manager.block_input_net_ids(block).empty()) { + fp << "\t\n"; + fp << "\t\t\n"; + for (const AtomNetId& net : bitstream_manager.block_input_net_ids(block)) { + if (false == atom_ctx.nlist.valid_net_id(net)) { + fp << " unmapped"; + } else { + VTR_ASSERT_SAFE(true == atom_ctx.nlist.valid_net_id(net)); + fp << " " << atom_ctx.nlist.net_name(net); + } + } + fp << "\n"; + fp << "\t\n"; + } + + if (false == bitstream_manager.block_output_net_ids(block).empty()) { + fp << "\t\n"; + fp << "\t\t\n"; + for (const AtomNetId& net : bitstream_manager.block_output_net_ids(block)) { + if (false == atom_ctx.nlist.valid_net_id(net)) { + fp << " unmapped"; + } else { + VTR_ASSERT_SAFE(true == atom_ctx.nlist.valid_net_id(net)); + fp << " " << atom_ctx.nlist.net_name(net); + } + } + fp << "\n"; + fp << "\t\n"; + } + /* Output child bits under this block */ size_t bit_counter = 0; fp << "\t" << std::endl; + for (const ConfigBitId& child_bit : bitstream_manager.block_bits(block)) { fp << "\t\t +#include "vpr_context.h" #include "bitstream_manager.h" /******************************************************************** @@ -15,6 +16,7 @@ namespace openfpga { void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstream_manager, + const AtomContext& clustering_ctx, const std::string& fname); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/bitstream_manager.cpp b/openfpga/src/fpga_bitstream/bitstream_manager.cpp index aaa3a384f..15946c292 100644 --- a/openfpga/src/fpga_bitstream/bitstream_manager.cpp +++ b/openfpga/src/fpga_bitstream/bitstream_manager.cpp @@ -115,6 +115,20 @@ int BitstreamManager::block_path_id(const ConfigBlockId& block_id) const { return block_path_ids_[block_id]; } +std::vector BitstreamManager::block_input_net_ids(const ConfigBlockId& block_id) const { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_block_id(block_id)); + + return block_input_net_ids_[block_id]; +} + +std::vector BitstreamManager::block_output_net_ids(const ConfigBlockId& block_id) const { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_block_id(block_id)); + + return block_output_net_ids_[block_id]; +} + /****************************************************************************** * Public Mutators ******************************************************************************/ @@ -136,6 +150,8 @@ ConfigBlockId BitstreamManager::add_block(const std::string& block_name) { block_names_.push_back(block_name); block_bit_ids_.emplace_back(); block_path_ids_.push_back(-2); + block_input_net_ids_.emplace_back(); + block_output_net_ids_.emplace_back(); parent_block_ids_.push_back(ConfigBlockId::INVALID()); child_block_ids_.emplace_back(); @@ -182,6 +198,24 @@ void BitstreamManager::add_path_id_to_block(const ConfigBlockId& block, const in block_path_ids_[block] = path_id; } +void BitstreamManager::add_input_net_id_to_block(const ConfigBlockId& block, + const AtomNetId& input_net_id) { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_block_id(block)); + + /* Add the bit to the block */ + block_input_net_ids_[block].push_back(input_net_id); +} + +void BitstreamManager::add_output_net_id_to_block(const ConfigBlockId& block, + const AtomNetId& output_net_id) { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_block_id(block)); + + /* Add the bit to the block */ + block_output_net_ids_[block].push_back(output_net_id); +} + void BitstreamManager::add_shared_config_bit_values(const ConfigBitId& bit, const std::vector& shared_config_bits) { /* Ensure the input ids are valid */ VTR_ASSERT(true == valid_bit_id(bit)); diff --git a/openfpga/src/fpga_bitstream/bitstream_manager.h b/openfpga/src/fpga_bitstream/bitstream_manager.h index 4ed2570bd..0621a214e 100644 --- a/openfpga/src/fpga_bitstream/bitstream_manager.h +++ b/openfpga/src/fpga_bitstream/bitstream_manager.h @@ -38,6 +38,9 @@ #include #include "vtr_vector.h" +/* Header files from vpr library */ +#include "atom_netlist_fwd.h" + #include "bitstream_manager_fwd.h" /* begin namespace openfpga */ @@ -85,6 +88,12 @@ class BitstreamManager { /* Find path id of a block */ int block_path_id(const ConfigBlockId& block_id) const; + /* Find input net ids of a block */ + std::vector block_input_net_ids(const ConfigBlockId& block_id) const; + + /* Find input net ids of a block */ + std::vector block_output_net_ids(const ConfigBlockId& block_id) const; + public: /* Public Mutators */ /* Add a new configuration bit to the bitstream manager */ ConfigBitId add_bit(const bool& bit_value); @@ -101,6 +110,12 @@ class BitstreamManager { /* Add a path id to a block */ void add_path_id_to_block(const ConfigBlockId& block, const int& path_id); + /* Add an input net id to a block */ + void add_input_net_id_to_block(const ConfigBlockId& block, const AtomNetId& input_net_id); + + /* Add an output net id to a block */ + void add_output_net_id_to_block(const ConfigBlockId& block, const AtomNetId& output_net_id); + /* Add share configuration bits to a configuration bit */ void add_shared_config_bit_values(const ConfigBitId& bit, const std::vector& shared_config_bits); @@ -126,8 +141,29 @@ class BitstreamManager { vtr::vector block_names_; vtr::vector parent_block_ids_; vtr::vector> child_block_ids_; + + /* The ids of the inputs of routing multiplexer blocks which is propagated to outputs + * By default, it will be -2 (which is invalid) + * A valid id starts from -1 + * -1 indicates an unused routing multiplexer. + * It will be converted to a valid id by bitstream builders) + * For used routing multiplexers, the path id will be >= 0 + * + * Note: + * -Bitstream manager will NOT check if the id is good for bitstream builders + * It just store the results + */ vtr::vector block_path_ids_; + /* Net ids that are mapped to inputs and outputs of this block + * + * Note: + * -Bitstream manager will NOT check if the id is good for bitstream builders + * It just store the results + */ + vtr::vector> block_input_net_ids_; + vtr::vector> block_output_net_ids_; + /* Unique id of a bit in the Bitstream */ vtr::vector bit_ids_; vtr::vector bit_parent_block_ids_; diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp index a5cde4853..a6e0a6bf3 100644 --- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp @@ -72,6 +72,7 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx, openfpga_ctx.module_graph(), openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), + vpr_ctx.atom(), openfpga_ctx.vpr_device_annotation(), openfpga_ctx.vpr_routing_annotation(), vpr_ctx.device().rr_graph, diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index 2d31fb2bc..fd09e3581 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -157,6 +157,10 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag size_t datapath_mux_size = fan_in; VTR_ASSERT(true == valid_mux_implementation_num_inputs(datapath_mux_size)); + /* Cache input and output nets */ + std::vector input_nets; + AtomNetId output_net = AtomNetId::INVALID(); + /* Find the path id: * - if des pb is not valid, this is an unmapped pb, we can set a default path_id * - There is no net mapped to des_pb_graph_pin we use default path id @@ -169,12 +173,19 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag } else if (AtomNetId::INVALID() == physical_pb.pb_graph_pin_atom_net(des_pb_id, des_pb_graph_pin)) { mux_input_pin_id = DEFAULT_PATH_ID; } else { + output_net = physical_pb.pb_graph_pin_atom_net(des_pb_id, des_pb_graph_pin); + + for (t_pb_graph_pin* src_pb_graph_pin : pb_graph_pin_inputs(des_pb_graph_pin, cur_interc)) { + const PhysicalPbId& src_pb_id = physical_pb.find_pb(src_pb_graph_pin->parent_node); + input_nets.push_back(physical_pb.pb_graph_pin_atom_net(src_pb_id, src_pb_graph_pin)); + } + for (t_pb_graph_pin* src_pb_graph_pin : pb_graph_pin_inputs(des_pb_graph_pin, cur_interc)) { const PhysicalPbId& src_pb_id = physical_pb.find_pb(src_pb_graph_pin->parent_node); /* If the src pb id is not valid, we bypass it */ if ( (true == physical_pb.valid_pb_id(src_pb_id)) - && (AtomNetId::INVALID() != physical_pb.pb_graph_pin_atom_net(des_pb_id, des_pb_graph_pin)) - && (physical_pb.pb_graph_pin_atom_net(src_pb_id, src_pb_graph_pin) == physical_pb.pb_graph_pin_atom_net(des_pb_id, des_pb_graph_pin))) { + && (AtomNetId::INVALID() != output_net) + && (physical_pb.pb_graph_pin_atom_net(src_pb_id, src_pb_graph_pin) == output_net)) { break; } mux_input_pin_id++; @@ -207,8 +218,13 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag /* Link the memory bits to the mux mem block */ bitstream_manager.add_bit_to_block(mux_mem_block, config_bit); } - /* Record path ids */ + /* Record path ids, input and output nets */ bitstream_manager.add_path_id_to_block(mux_mem_block, mux_input_pin_id); + for (const AtomNetId& input_net : input_nets) { + bitstream_manager.add_input_net_id_to_block(mux_mem_block, input_net); + } + bitstream_manager.add_output_net_id_to_block(mux_mem_block, output_net); + break; } default: diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp index 5b5e38c7d..d7a23039a 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp @@ -41,6 +41,7 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager, const RRGraph& rr_graph, const RRNodeId& cur_rr_node, const std::vector& drive_rr_nodes, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation) { /* Check current rr_node is CHANX or CHANY*/ @@ -50,15 +51,23 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager, /* Find the input size of the implementation of a routing multiplexer */ size_t datapath_mux_size = drive_rr_nodes.size(); + /* Cache input and output nets */ + std::vector input_nets; + ClusterNetId output_net = routing_annotation.rr_node_net(cur_rr_node); + for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) { + input_nets.push_back(routing_annotation.rr_node_net(drive_rr_nodes[inode])); + } + VTR_ASSERT(input_nets.size() == drive_rr_nodes.size()); + /* Find out which routing path is used in this MUX * Two conditions to be considered: * - There is no net mapped to cur_rr_node: we use default path id * - There is a net mapped to cur_rr_node: we find the path id */ int path_id = DEFAULT_PATH_ID; - if (ClusterNetId::INVALID() != routing_annotation.rr_node_net(cur_rr_node)) { + if (ClusterNetId::INVALID() != output_net) { for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) { - if (routing_annotation.rr_node_net(drive_rr_nodes[inode]) == routing_annotation.rr_node_net(cur_rr_node)) { + if (input_nets[inode] == output_net) { path_id = (int)inode; break; } @@ -91,8 +100,14 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager, /* Link the memory bits to the mux mem block */ bitstream_manager.add_bit_to_block(mux_mem_block, config_bit); } - /* Record path ids */ + /* Record path ids, input and output nets */ bitstream_manager.add_path_id_to_block(mux_mem_block, path_id); + for (const ClusterNetId& input_net : input_nets) { + AtomNetId input_atom_net = atom_ctx.lookup.atom_net(input_net); + bitstream_manager.add_input_net_id_to_block(mux_mem_block, input_atom_net); + } + AtomNetId output_atom_net = atom_ctx.lookup.atom_net(output_net); + bitstream_manager.add_output_net_id_to_block(mux_mem_block, output_atom_net); } /******************************************************************** @@ -109,6 +124,7 @@ void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const RRGraph& rr_graph, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGSB& rr_gsb, @@ -142,7 +158,7 @@ void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager, build_switch_block_mux_bitstream(bitstream_manager, mux_mem_block, module_manager, circuit_lib, mux_lib, rr_graph, cur_rr_node, driver_rr_nodes, - device_annotation, routing_annotation); + atom_ctx, device_annotation, routing_annotation); } /*Nothing should be done else*/ } @@ -163,6 +179,7 @@ void build_switch_block_bitstream(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraph& rr_graph, @@ -181,7 +198,7 @@ void build_switch_block_bitstream(BitstreamManager& bitstream_manager, build_switch_block_interc_bitstream(bitstream_manager, sb_config_block, module_manager, circuit_lib, mux_lib, rr_graph, - device_annotation, routing_annotation, + atom_ctx, device_annotation, routing_annotation, rr_gsb, side_manager.get_side(), itrack); } } @@ -200,6 +217,7 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraph& rr_graph, @@ -208,6 +226,14 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager, /* Find drive_rr_nodes*/ size_t datapath_mux_size = rr_graph.node_fan_in(src_rr_node); + /* Cache input and output nets */ + std::vector input_nets; + ClusterNetId output_net = routing_annotation.rr_node_net(src_rr_node); + for (const RREdgeId& edge : rr_graph.node_in_edges(src_rr_node)) { + RRNodeId driver_node = rr_graph.edge_src_node(edge); + input_nets.push_back(routing_annotation.rr_node_net(driver_node)); + } + /* Configuration bits for MUX*/ int path_id = DEFAULT_PATH_ID; int edge_index = 0; @@ -217,10 +243,10 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager, * - There is no net mapped to src_rr_node: we use default path id * - There is a net mapped to src_rr_node: we find the path id */ - if (ClusterNetId::INVALID() != routing_annotation.rr_node_net(src_rr_node)) { + if (ClusterNetId::INVALID() != output_net) { for (const RREdgeId& edge : rr_graph.node_in_edges(src_rr_node)) { RRNodeId driver_node = rr_graph.edge_src_node(edge); - if (routing_annotation.rr_node_net(driver_node) == routing_annotation.rr_node_net(src_rr_node)) { + if (routing_annotation.rr_node_net(driver_node) == output_net) { path_id = edge_index; break; } @@ -254,8 +280,14 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager, /* Link the memory bits to the mux mem block */ bitstream_manager.add_bit_to_block(mux_mem_block, config_bit); } - /* Record path ids */ + /* Record path ids, input and output nets */ bitstream_manager.add_path_id_to_block(mux_mem_block, path_id); + for (const ClusterNetId& input_net : input_nets) { + AtomNetId input_atom_net = atom_ctx.lookup.atom_net(input_net); + bitstream_manager.add_input_net_id_to_block(mux_mem_block, input_atom_net); + } + AtomNetId output_atom_net = atom_ctx.lookup.atom_net(output_net); + bitstream_manager.add_output_net_id_to_block(mux_mem_block, output_atom_net); } @@ -272,6 +304,7 @@ void build_connection_block_interc_bitstream(BitstreamManager& bitstream_manager const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraph& rr_graph, @@ -294,7 +327,7 @@ void build_connection_block_interc_bitstream(BitstreamManager& bitstream_manager /* This is a routing multiplexer! Generate bitstream */ build_connection_block_mux_bitstream(bitstream_manager, mux_mem_block, module_manager, circuit_lib, mux_lib, - device_annotation, routing_annotation, + atom_ctx, device_annotation, routing_annotation, rr_graph, src_rr_node); } /*Nothing should be done else*/ } @@ -316,6 +349,7 @@ void build_connection_block_bitstream(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraph& rr_graph, @@ -331,7 +365,7 @@ void build_connection_block_bitstream(BitstreamManager& bitstream_manager, for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { build_connection_block_interc_bitstream(bitstream_manager, cb_configurable_block, module_manager, circuit_lib, mux_lib, - device_annotation, routing_annotation, + atom_ctx, device_annotation, routing_annotation, rr_graph, rr_gsb, cb_ipin_side, inode); } @@ -347,6 +381,7 @@ void build_connection_block_bitstreams(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraph& rr_graph, @@ -377,7 +412,7 @@ void build_connection_block_bitstreams(BitstreamManager& bitstream_manager, build_connection_block_bitstream(bitstream_manager, cb_configurable_block, module_manager, circuit_lib, mux_lib, - device_annotation, routing_annotation, + atom_ctx, device_annotation, routing_annotation, rr_graph, rr_gsb, cb_type); } @@ -395,6 +430,7 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraph& rr_graph, @@ -425,7 +461,7 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager, build_switch_block_bitstream(bitstream_manager, sb_configurable_block, module_manager, circuit_lib, mux_lib, - device_annotation, routing_annotation, + atom_ctx, device_annotation, routing_annotation, rr_graph, rr_gsb); } @@ -440,7 +476,7 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager, build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager, circuit_lib, mux_lib, - device_annotation, routing_annotation, + atom_ctx, device_annotation, routing_annotation, rr_graph, device_rr_gsb, CHANX); VTR_LOG("Done\n"); @@ -449,7 +485,7 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager, build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager, circuit_lib, mux_lib, - device_annotation, routing_annotation, + atom_ctx, device_annotation, routing_annotation, rr_graph, device_rr_gsb, CHANY); VTR_LOG("Done\n"); diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.h b/openfpga/src/fpga_bitstream/build_routing_bitstream.h index 2337601fe..c98e6e32e 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.h +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.h @@ -29,6 +29,7 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraph& rr_graph, From 4f7e8020a878d4f202c420558aeb70676099e406 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jun 2020 00:08:28 -0600 Subject: [PATCH 24/35] minor fix on the format of arch bitstream writer --- .../src/fpga_bitstream/arch_bitstream_writer.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp b/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp index 3006a6db6..6b3afdf4b 100644 --- a/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp +++ b/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp @@ -84,13 +84,13 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp, /* Output input/output nets if there are any */ if (false == bitstream_manager.block_input_net_ids(block).empty()) { fp << "\t\n"; - fp << "\t\t\n"; + fp << "\t\t"; for (const AtomNetId& net : bitstream_manager.block_input_net_ids(block)) { if (false == atom_ctx.nlist.valid_net_id(net)) { - fp << " unmapped"; + fp << "\tunmapped"; } else { VTR_ASSERT_SAFE(true == atom_ctx.nlist.valid_net_id(net)); - fp << " " << atom_ctx.nlist.net_name(net); + fp << "\t" << atom_ctx.nlist.net_name(net); } } fp << "\n"; @@ -99,13 +99,13 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp, if (false == bitstream_manager.block_output_net_ids(block).empty()) { fp << "\t\n"; - fp << "\t\t\n"; + fp << "\t\t"; for (const AtomNetId& net : bitstream_manager.block_output_net_ids(block)) { if (false == atom_ctx.nlist.valid_net_id(net)) { - fp << " unmapped"; + fp << "\tunmapped"; } else { VTR_ASSERT_SAFE(true == atom_ctx.nlist.valid_net_id(net)); - fp << " " << atom_ctx.nlist.net_name(net); + fp << "\t" << atom_ctx.nlist.net_name(net); } } fp << "\n"; From 5d79a3f69fc43a61ec0ea34955a95f00ae605c04 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jun 2020 11:17:57 -0600 Subject: [PATCH 25/35] critical bug fixed when annotating the routing results. Add previous node check. This is due to that some loops between SB/CBs may exist when routing congestion is high, which leads to same nets appear in the inputs of a routing multiplexer. Actually one of them is driven by the other as a downstream node Using previous node check can identify which one to pick --- openfpga/src/annotation/annotate_routing.cpp | 129 ++++++++++++++++++ openfpga/src/annotation/annotate_routing.h | 6 + .../src/annotation/vpr_routing_annotation.cpp | 21 +++ .../src/annotation/vpr_routing_annotation.h | 8 +- openfpga/src/base/openfpga_link_arch.cpp | 9 +- .../build_routing_bitstream.cpp | 10 +- 6 files changed, 179 insertions(+), 4 deletions(-) diff --git a/openfpga/src/annotation/annotate_routing.cpp b/openfpga/src/annotation/annotate_routing.cpp index 5e9dc4144..1349c622c 100644 --- a/openfpga/src/annotation/annotate_routing.cpp +++ b/openfpga/src/annotation/annotate_routing.cpp @@ -50,5 +50,134 @@ void annotate_rr_node_nets(const DeviceContext& device_ctx, VTR_LOG("Done with %d nodes mapping\n", counter); } + +/******************************************************************** + * This function will find a previous node for a given rr_node + * from the routing traces + * + * It requires a candidate which provided by upstream functions + * Try to validate a candidate by searching it from driving node list + * If not validated, try to find a right one in the routing traces + *******************************************************************/ +static +RRNodeId find_previous_node_from_routing_traces(const RRGraph& rr_graph, + t_trace* routing_trace_head, + const RRNodeId& prev_node_candidate, + const RRNodeId& cur_rr_node) { + RRNodeId prev_node = prev_node_candidate; + + /* For a valid prev_node, ensure prev node is one of the driving nodes for this rr_node! */ + if (prev_node) { + /* Try to spot the previous node in the incoming node list of this rr_node */ + bool valid_prev_node = false; + for (const RREdgeId& in_edge : rr_graph.node_in_edges(cur_rr_node)) { + if (prev_node == rr_graph.edge_src_node(in_edge)) { + valid_prev_node = true; + break; + } + } + + /* Early exit if we already validate the node */ + if (true == valid_prev_node) { + return prev_node; + } + + /* If we cannot find one, it could be possible that this rr_node branches + * from an earlier point in the routing tree + * + * +----- ... --->prev_node + * | + * src_node->+ + * | + * +-----+ rr_node + * + * Our job now is to start from the head of the traces and find the prev_node + * that drives this rr_node + * + * This search will find the first-fit and finish. + * This is reasonable because if there is a second-fit, it should be a longer path + * which should be considered in routing optimization + */ + if (false == valid_prev_node) { + t_trace* tptr = routing_trace_head; + while (tptr != nullptr) { + RRNodeId cand_prev_node = tptr->index; + bool is_good_cand = false; + for (const RREdgeId& in_edge : rr_graph.node_in_edges(cur_rr_node)) { + if (cand_prev_node == rr_graph.edge_src_node(in_edge)) { + is_good_cand = true; + break; + } + } + + if (true == is_good_cand) { + /* Update prev_node */ + prev_node = cand_prev_node; + break; + } + + /* Move on to the next */ + tptr = tptr->next; + } + } + } + + return prev_node; +} + +/******************************************************************** + * Create a mapping between each rr_node and its previous node + * based on VPR routing results + * - Unmapped rr_node will have an invalid id of previous rr_node + *******************************************************************/ +void annotate_rr_node_previous_nodes(const DeviceContext& device_ctx, + const ClusteringContext& clustering_ctx, + const RoutingContext& routing_ctx, + VprRoutingAnnotation& vpr_routing_annotation, + const bool& verbose) { + size_t counter = 0; + VTR_LOG("Annotating previous nodes for rr_node..."); + VTR_LOGV(verbose, "\n"); + + for (auto net_id : clustering_ctx.clb_nlist.nets()) { + /* Ignore nets that are not routed */ + if (true == clustering_ctx.clb_nlist.net_is_ignored(net_id)) { + continue; + } + /* Ignore used in local cluster only, reserved one CLB pin */ + if (false == clustering_ctx.clb_nlist.net_sinks(net_id).size()) { + continue; + } + + /* Cache Previous nodes */ + RRNodeId prev_node = RRNodeId::INVALID(); + + t_trace* tptr = routing_ctx.trace[net_id].head; + while (tptr != nullptr) { + RRNodeId rr_node = tptr->index; + + /* Find the right previous node */ + prev_node = find_previous_node_from_routing_traces(device_ctx.rr_graph, + routing_ctx.trace[net_id].head, + prev_node, + rr_node); + + /* Only update mapped nodes */ + if (prev_node) { + vpr_routing_annotation.set_rr_node_prev_node(rr_node, prev_node); + counter++; + } + + /* Update prev_node */ + prev_node = rr_node; + + /* Move on to the next */ + tptr = tptr->next; + } + } + + VTR_LOG("Done with %d nodes mapping\n", counter); +} + } /* end namespace openfpga */ diff --git a/openfpga/src/annotation/annotate_routing.h b/openfpga/src/annotation/annotate_routing.h index 9496c6e81..a754e6fe7 100644 --- a/openfpga/src/annotation/annotate_routing.h +++ b/openfpga/src/annotation/annotate_routing.h @@ -21,6 +21,12 @@ void annotate_rr_node_nets(const DeviceContext& device_ctx, VprRoutingAnnotation& vpr_routing_annotation, const bool& verbose); +void annotate_rr_node_previous_nodes(const DeviceContext& device_ctx, + const ClusteringContext& clustering_ctx, + const RoutingContext& routing_ctx, + VprRoutingAnnotation& vpr_routing_annotation, + const bool& verbose); + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/annotation/vpr_routing_annotation.cpp b/openfpga/src/annotation/vpr_routing_annotation.cpp index b51f4be94..e0014638f 100644 --- a/openfpga/src/annotation/vpr_routing_annotation.cpp +++ b/openfpga/src/annotation/vpr_routing_annotation.cpp @@ -24,11 +24,18 @@ ClusterNetId VprRoutingAnnotation::rr_node_net(const RRNodeId& rr_node) const { return rr_node_nets_[rr_node]; } +RRNodeId VprRoutingAnnotation::rr_node_prev_node(const RRNodeId& rr_node) const { + /* Ensure that the node_id is in the list */ + VTR_ASSERT(size_t(rr_node) < rr_node_nets_.size()); + return rr_node_prev_nodes_[rr_node]; +} + /************************************************************************ * Public mutators ***********************************************************************/ void VprRoutingAnnotation::init(const RRGraph& rr_graph) { rr_node_nets_.resize(rr_graph.nodes().size(), ClusterNetId::INVALID()); + rr_node_prev_nodes_.resize(rr_graph.nodes().size(), RRNodeId::INVALID()); } void VprRoutingAnnotation::set_rr_node_net(const RRNodeId& rr_node, @@ -45,4 +52,18 @@ void VprRoutingAnnotation::set_rr_node_net(const RRNodeId& rr_node, rr_node_nets_[rr_node] = net_id; } +void VprRoutingAnnotation::set_rr_node_prev_node(const RRNodeId& rr_node, + const RRNodeId& prev_node) { + /* Ensure that the node_id is in the list */ + VTR_ASSERT(size_t(rr_node) < rr_node_nets_.size()); + /* Warn any override attempt */ + if ( (RRNodeId::INVALID() != rr_node_prev_nodes_[rr_node]) + && (prev_node != rr_node_prev_nodes_[rr_node])) { + VTR_LOG_WARN("Override the previous node '%ld' by previous node '%ld' for node '%ld' with in routing context annotation!\n", + size_t(rr_node_prev_nodes_[rr_node]), size_t(prev_node), size_t(rr_node)); + } + + rr_node_prev_nodes_[rr_node] = prev_node; +} + } /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/vpr_routing_annotation.h b/openfpga/src/annotation/vpr_routing_annotation.h index 5508ae3b0..e22f04e5b 100644 --- a/openfpga/src/annotation/vpr_routing_annotation.h +++ b/openfpga/src/annotation/vpr_routing_annotation.h @@ -26,13 +26,19 @@ class VprRoutingAnnotation { VprRoutingAnnotation(); public: /* Public accessors */ ClusterNetId rr_node_net(const RRNodeId& rr_node) const; + RRNodeId rr_node_prev_node(const RRNodeId& rr_node) const; public: /* Public mutators */ void init(const RRGraph& rr_graph); void set_rr_node_net(const RRNodeId& rr_node, const ClusterNetId& net_id); + void set_rr_node_prev_node(const RRNodeId& rr_node, + const RRNodeId& prev_node); private: /* Internal data */ - /* Pair a regular pb_type to its physical pb_type */ + /* Clustered net ids mapped to each rr_node */ vtr::vector rr_node_nets_; + + /* Previous rr_node driving each rr_node */ + vtr::vector rr_node_prev_nodes_; }; } /* End namespace openfpga*/ diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp index af75ff6a2..ff8bd6151 100644 --- a/openfpga/src/base/openfpga_link_arch.cpp +++ b/openfpga/src/base/openfpga_link_arch.cpp @@ -95,7 +95,9 @@ int link_arch(OpenfpgaContext& openfpga_ctx, openfpga_ctx.mutable_vpr_device_annotation(), cmd_context.option_enable(cmd, opt_verbose)); - /* Annotate net mapping to each rr_node + /* Annotate routing results: + * - net mapping to each rr_node + * - previous nodes driving each rr_node */ openfpga_ctx.mutable_vpr_routing_annotation().init(g_vpr_ctx.device().rr_graph); @@ -103,6 +105,11 @@ int link_arch(OpenfpgaContext& openfpga_ctx, openfpga_ctx.mutable_vpr_routing_annotation(), cmd_context.option_enable(cmd, opt_verbose)); + annotate_rr_node_previous_nodes(g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.routing(), + openfpga_ctx.mutable_vpr_routing_annotation(), + cmd_context.option_enable(cmd, opt_verbose)); + + /* Build the routing graph annotation * - RRGSB * - DeviceRRGSB diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp index d7a23039a..b396385a0 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp @@ -66,8 +66,11 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager, */ int path_id = DEFAULT_PATH_ID; if (ClusterNetId::INVALID() != output_net) { + /* We must have a valid previous node that is supposed to drive the source node! */ + VTR_ASSERT(routing_annotation.rr_node_prev_node(cur_rr_node)); for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) { - if (input_nets[inode] == output_net) { + if ( (input_nets[inode] == output_net) + && (drive_rr_nodes[inode] == routing_annotation.rr_node_prev_node(cur_rr_node)) ) { path_id = (int)inode; break; } @@ -246,7 +249,10 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager, if (ClusterNetId::INVALID() != output_net) { for (const RREdgeId& edge : rr_graph.node_in_edges(src_rr_node)) { RRNodeId driver_node = rr_graph.edge_src_node(edge); - if (routing_annotation.rr_node_net(driver_node) == output_net) { + /* We must have a valid previous node that is supposed to drive the source node! */ + VTR_ASSERT(routing_annotation.rr_node_prev_node(src_rr_node)); + if ( (routing_annotation.rr_node_net(driver_node) == output_net) + && (driver_node == routing_annotation.rr_node_prev_node(src_rr_node)) ) { path_id = edge_index; break; } From 91b072d7c59867222e528508c8c2f005adf7f017 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jun 2020 11:56:40 -0600 Subject: [PATCH 26/35] documentation update on the bitstream file format to synchronize with the latest codes --- .../fpga_bitstream/generic_bitstream.rst | 47 ++++++++++++++++++- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/docs/source/manual/fpga_bitstream/generic_bitstream.rst b/docs/source/manual/fpga_bitstream/generic_bitstream.rst index 78fbd3de4..7d4bebffa 100644 --- a/docs/source/manual/fpga_bitstream/generic_bitstream.rst +++ b/docs/source/manual/fpga_bitstream/generic_bitstream.rst @@ -6,23 +6,44 @@ Usage Generic bitstream is a fabric-independent bitstream where configuration bits are organized out-of-order in a database. This can be regarded as a raw bitstream used for + - ``debugging``: Hardware engineers can validate if their configuration memories across the FPGA fabric are assigned to expected values + - ``an exchangeable file format for bitstream assembler``: Software engineers can use the raw bitstream to build a bitstream assembler which organize the bitstream in the loadable formate to FPGA chips. + - ``creation of artificial bitstream``: Test engineers can craft artificial bitstreams to test each element of the FPGA fabric, which is typically not synthesizable by VPR. -.. note:: The fabric-independent bitstream cannot be directly loaded to FPGA fabrics +.. warning:: The fabric-independent bitstream cannot be directly loaded to FPGA fabrics File Format ``````````` -OpenFPGA can output the generic bitstream to an XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes two sets of information: +OpenFPGA can output the generic bitstream to an XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes the follwoing information: - ``hierarchy`` represents the location of this block in FPGA fabric. + The hierachy includes the full hierarchy of this block + + - ``instance`` denotes the instance name which you can find in the fabric netlists + + - ``level`` denotes the depth of the block in the hierarchy + + - ``input_nets`` represents the net names that are mapped to the inputs of block. Unused inputs will be tagged as ``unmapped`` which is a reserved word of OpenFPGA. + + - ``output_nets`` represents the net names that are mapped to the outputs of block. Unused outputs will be tagged as ``unmapped`` which is a reserved word OpenFPGA. - ``bitstream`` represents the configuration bits affiliated to this block. + - ``path_id`` denotes the index of inputs which is propagated to the output. Note that smallest valid index starts from zero. Only routing multiplexers have the path index. Unused routing multiplexer will not have a ``path_id`` of ``-1``, which allows bitstream assembler to freely find the best path in terms of Quality of Results (QoR). A used routing multiplexer should have a zero or positive ``path_id``. + + - ``bit`` denotes a single configuration bit under this block. It contains \ + + - ``memory_port`` the memory port name which you can find in the fabric netlists by following the hierarchy. + + - ``value`` a binary value which is the configuration bit assigned to the memory port. + .. code-block:: xml + @@ -49,3 +70,25 @@ OpenFPGA can output the generic bitstream to an XML format, which is easy to deb + + + + + + + + + + + + SAP_out[1] SAP_out[1] + + + SAP_out[1] + + + + + + + From 675a59ecb8fa523fa0209c6e633207aaeb09731a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 20 Jun 2020 18:25:17 -0600 Subject: [PATCH 27/35] Move fpga_bitstream to the libopenfpga library and add XML reader --- libopenfpga/CMakeLists.txt | 1 + libopenfpga/libfpgabitstream/CMakeLists.txt | 35 ++++ .../src}/arch_bitstream_writer.cpp | 92 +++++---- .../src}/arch_bitstream_writer.h | 3 +- .../src}/bitstream_manager.cpp | 37 +++- .../libfpgabitstream/src}/bitstream_manager.h | 25 ++- .../src}/bitstream_manager_fwd.h | 0 .../src}/bitstream_manager_utils.cpp | 0 .../src}/bitstream_manager_utils.h | 0 .../src/read_xml_arch_bitstream.cpp | 181 ++++++++++++++++++ .../src/read_xml_arch_bitstream.h | 21 ++ .../test/test_arch_bitstream.cpp | 33 ++++ .../libopenfpgautil/src/openfpga_digest.cpp | 16 ++ .../libopenfpgautil/src/openfpga_digest.h | 3 + .../src}/openfpga_reserved_words.h | 5 + openfpga/CMakeLists.txt | 1 + openfpga/src/base/openfpga_bitstream.cpp | 3 +- openfpga/src/base/openfpga_naming.cpp | 6 +- .../fpga_bitstream/build_device_bitstream.cpp | 1 + .../fpga_bitstream/build_grid_bitstream.cpp | 36 +++- .../src/fpga_bitstream/build_grid_bitstream.h | 2 + .../build_routing_bitstream.cpp | 25 ++- 22 files changed, 455 insertions(+), 71 deletions(-) create mode 100644 libopenfpga/libfpgabitstream/CMakeLists.txt rename {openfpga/src/fpga_bitstream => libopenfpga/libfpgabitstream/src}/arch_bitstream_writer.cpp (70%) rename {openfpga/src/fpga_bitstream => libopenfpga/libfpgabitstream/src}/arch_bitstream_writer.h (87%) rename {openfpga/src/fpga_bitstream => libopenfpga/libfpgabitstream/src}/bitstream_manager.cpp (87%) rename {openfpga/src/fpga_bitstream => libopenfpga/libfpgabitstream/src}/bitstream_manager.h (90%) rename {openfpga/src/fpga_bitstream => libopenfpga/libfpgabitstream/src}/bitstream_manager_fwd.h (100%) rename {openfpga/src/fpga_bitstream => libopenfpga/libfpgabitstream/src}/bitstream_manager_utils.cpp (100%) rename {openfpga/src/fpga_bitstream => libopenfpga/libfpgabitstream/src}/bitstream_manager_utils.h (100%) create mode 100644 libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.cpp create mode 100644 libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.h create mode 100644 libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp rename {openfpga/src/base => libopenfpga/libopenfpgautil/src}/openfpga_reserved_words.h (93%) diff --git a/libopenfpga/CMakeLists.txt b/libopenfpga/CMakeLists.txt index ec3299198..92d25522a 100644 --- a/libopenfpga/CMakeLists.txt +++ b/libopenfpga/CMakeLists.txt @@ -4,3 +4,4 @@ add_subdirectory(libopenfpgashell) add_subdirectory(libarchopenfpga) add_subdirectory(libopenfpgautil) add_subdirectory(libfabrickey) +add_subdirectory(libfpgabitstream) diff --git a/libopenfpga/libfpgabitstream/CMakeLists.txt b/libopenfpga/libfpgabitstream/CMakeLists.txt new file mode 100644 index 000000000..ce1a37d31 --- /dev/null +++ b/libopenfpga/libfpgabitstream/CMakeLists.txt @@ -0,0 +1,35 @@ +cmake_minimum_required(VERSION 3.9) + +project("libfpgabitstream") + +file(GLOB_RECURSE EXEC_SOURCES test/*.cpp) +file(GLOB_RECURSE LIB_SOURCES src/*.cpp) +file(GLOB_RECURSE LIB_HEADERS src/*.h) +files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS) + +#Remove test executable from library +list(REMOVE_ITEM LIB_SOURCES ${EXEC_SOURCES}) + +#Create the library +add_library(libfpgabitstream STATIC + ${LIB_HEADERS} + ${LIB_SOURCES}) +target_include_directories(libfpgabitstream PUBLIC ${LIB_INCLUDE_DIRS}) +set_target_properties(libfpgabitstream PROPERTIES PREFIX "") #Avoid extra 'lib' prefix + +#Specify link-time dependancies +target_link_libraries(libfpgabitstream + libopenfpgautil + libarchopenfpga + libvtrutil + libpugixml + libpugiutil) + +#Create the test executable +foreach(testsourcefile ${EXEC_SOURCES}) + # Use a simple string replace, to cut off .cpp. + get_filename_component(testname ${testsourcefile} NAME_WE) + add_executable(${testname} ${testsourcefile}) + # Make sure the library is linked to each test executable + target_link_libraries(${testname} libfpgabitstream) +endforeach(testsourcefile ${EXEC_SOURCES}) diff --git a/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp b/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp similarity index 70% rename from openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp rename to libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp index 6b3afdf4b..ebb0a3129 100644 --- a/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp +++ b/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp @@ -14,7 +14,7 @@ /* Headers from openfpgautil library */ #include "openfpga_digest.h" -#include "openfpga_naming.h" +#include "openfpga_reserved_words.h" #include "bitstream_manager_utils.h" #include "arch_bitstream_writer.h" @@ -51,70 +51,86 @@ void write_bitstream_xml_file_head(std::fstream& fp) { *******************************************************************/ static void rec_write_block_bitstream_to_xml_file(std::fstream& fp, - const AtomContext& atom_ctx, const BitstreamManager& bitstream_manager, - const ConfigBlockId& block) { + const ConfigBlockId& block, + const size_t& hierarchy_level) { valid_file_stream(fp); + /* Write the bits of this block */ + write_tab_to_file(fp, hierarchy_level); + fp << "" << std::endl; + /* Dive to child blocks if this block has any */ for (const ConfigBlockId& child_block : bitstream_manager.block_children(block)) { - rec_write_block_bitstream_to_xml_file(fp, atom_ctx, bitstream_manager, child_block); + rec_write_block_bitstream_to_xml_file(fp, bitstream_manager, child_block, hierarchy_level + 1); } if (0 == bitstream_manager.block_bits(block).size()) { + write_tab_to_file(fp, hierarchy_level); + fp << "" <" << std::endl; - std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, block); /* Output hierarchy of this parent*/ - fp << "\t" << std::endl; + write_tab_to_file(fp, hierarchy_level + 1); + fp << "" << std::endl; size_t hierarchy_counter = 0; for (const ConfigBlockId& temp_block : block_hierarchy) { - fp << "\t\t" << std::endl; hierarchy_counter++; } - fp << "\t" << std::endl; + write_tab_to_file(fp, hierarchy_level + 1); + fp << "" << std::endl; /* Output input/output nets if there are any */ if (false == bitstream_manager.block_input_net_ids(block).empty()) { - fp << "\t\n"; - fp << "\t\t"; - for (const AtomNetId& net : bitstream_manager.block_input_net_ids(block)) { - if (false == atom_ctx.nlist.valid_net_id(net)) { - fp << "\tunmapped"; - } else { - VTR_ASSERT_SAFE(true == atom_ctx.nlist.valid_net_id(net)); - fp << "\t" << atom_ctx.nlist.net_name(net); - } + write_tab_to_file(fp, hierarchy_level + 1); + fp << "\n"; + size_t path_counter = 0; + for (const std::string& net : bitstream_manager.block_input_net_ids(block)) { + write_tab_to_file(fp, hierarchy_level + 2); + fp << ""; + + path_counter++; } fp << "\n"; - fp << "\t\n"; + write_tab_to_file(fp, hierarchy_level + 1); + fp << "\n"; } if (false == bitstream_manager.block_output_net_ids(block).empty()) { - fp << "\t\n"; - fp << "\t\t"; - for (const AtomNetId& net : bitstream_manager.block_output_net_ids(block)) { - if (false == atom_ctx.nlist.valid_net_id(net)) { - fp << "\tunmapped"; - } else { - VTR_ASSERT_SAFE(true == atom_ctx.nlist.valid_net_id(net)); - fp << "\t" << atom_ctx.nlist.net_name(net); - } + write_tab_to_file(fp, hierarchy_level + 1); + fp << "\n"; + size_t path_counter = 0; + for (const std::string& net : bitstream_manager.block_output_net_ids(block)) { + write_tab_to_file(fp, hierarchy_level + 2); + fp << ""; + + path_counter++; } fp << "\n"; - fp << "\t\n"; + write_tab_to_file(fp, hierarchy_level + 1); + fp << "\n"; } /* Output child bits under this block */ size_t bit_counter = 0; - fp << "\t" << std::endl; for (const ConfigBitId& child_bit : bitstream_manager.block_bits(block)) { - fp << "\t\t" << std::endl; bit_counter++; } - fp << "\t" << std::endl; + write_tab_to_file(fp, hierarchy_level + 1); + fp << "" << std::endl; + write_tab_to_file(fp, hierarchy_level); fp << "" < top_block = find_bitstream_manager_top_blocks(bitstream_manager); /* Make sure we have only 1 top block and its name matches the top module */ @@ -175,7 +193,7 @@ void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstr VTR_ASSERT(0 == top_block_name.compare(bitstream_manager.block_name(top_block[0]))); /* Write bitstream, block by block, in a recursive way */ - rec_write_block_bitstream_to_xml_file(fp, atom_ctx, bitstream_manager, top_block[0]); + rec_write_block_bitstream_to_xml_file(fp, bitstream_manager, top_block[0], 0); /* Close file handler */ fp.close(); diff --git a/openfpga/src/fpga_bitstream/arch_bitstream_writer.h b/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.h similarity index 87% rename from openfpga/src/fpga_bitstream/arch_bitstream_writer.h rename to libopenfpga/libfpgabitstream/src/arch_bitstream_writer.h index 69ee1f5a2..91f9e271d 100644 --- a/openfpga/src/fpga_bitstream/arch_bitstream_writer.h +++ b/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.h @@ -5,7 +5,6 @@ * Include header files that are required by function declaration *******************************************************************/ #include -#include "vpr_context.h" #include "bitstream_manager.h" /******************************************************************** @@ -16,7 +15,7 @@ namespace openfpga { void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstream_manager, - const AtomContext& clustering_ctx, + const std::string& top_block_name, const std::string& fname); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/bitstream_manager.cpp b/libopenfpga/libfpgabitstream/src/bitstream_manager.cpp similarity index 87% rename from openfpga/src/fpga_bitstream/bitstream_manager.cpp rename to libopenfpga/libfpgabitstream/src/bitstream_manager.cpp index 15946c292..66b4d1f23 100644 --- a/openfpga/src/fpga_bitstream/bitstream_manager.cpp +++ b/libopenfpga/libfpgabitstream/src/bitstream_manager.cpp @@ -115,14 +115,14 @@ int BitstreamManager::block_path_id(const ConfigBlockId& block_id) const { return block_path_ids_[block_id]; } -std::vector BitstreamManager::block_input_net_ids(const ConfigBlockId& block_id) const { +std::vector BitstreamManager::block_input_net_ids(const ConfigBlockId& block_id) const { /* Ensure the input ids are valid */ VTR_ASSERT(true == valid_block_id(block_id)); return block_input_net_ids_[block_id]; } -std::vector BitstreamManager::block_output_net_ids(const ConfigBlockId& block_id) const { +std::vector BitstreamManager::block_output_net_ids(const ConfigBlockId& block_id) const { /* Ensure the input ids are valid */ VTR_ASSERT(true == valid_block_id(block_id)); @@ -143,11 +143,22 @@ ConfigBitId BitstreamManager::add_bit(const bool& bit_value) { return bit; } -ConfigBlockId BitstreamManager::add_block(const std::string& block_name) { +void BitstreamManager::reserve_blocks(const size_t& num_blocks) { + block_ids_.reserve(num_blocks); + block_names_.reserve(num_blocks); + block_bit_ids_.reserve(num_blocks); + block_path_ids_.reserve(num_blocks); + block_input_net_ids_.reserve(num_blocks); + block_output_net_ids_.reserve(num_blocks); + parent_block_ids_.reserve(num_blocks); + child_block_ids_.reserve(num_blocks); +} + +ConfigBlockId BitstreamManager::create_block() { ConfigBlockId block = ConfigBlockId(block_ids_.size()); /* Add a new bit, and allocate associated data structures */ block_ids_.push_back(block); - block_names_.push_back(block_name); + block_names_.emplace_back(); block_bit_ids_.emplace_back(); block_path_ids_.push_back(-2); block_input_net_ids_.emplace_back(); @@ -158,6 +169,20 @@ ConfigBlockId BitstreamManager::add_block(const std::string& block_name) { return block; } +ConfigBlockId BitstreamManager::add_block(const std::string& block_name) { + ConfigBlockId block = create_block(); + set_block_name(block, block_name); + + return block; +} + +void BitstreamManager::set_block_name(const ConfigBlockId& block_id, + const std::string& block_name) { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_block_id(block_id)); + block_names_[block_id] = block_name; +} + void BitstreamManager::add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block) { /* Ensure the input ids are valid */ VTR_ASSERT(true == valid_block_id(parent_block)); @@ -199,7 +224,7 @@ void BitstreamManager::add_path_id_to_block(const ConfigBlockId& block, const in } void BitstreamManager::add_input_net_id_to_block(const ConfigBlockId& block, - const AtomNetId& input_net_id) { + const std::string& input_net_id) { /* Ensure the input ids are valid */ VTR_ASSERT(true == valid_block_id(block)); @@ -208,7 +233,7 @@ void BitstreamManager::add_input_net_id_to_block(const ConfigBlockId& block, } void BitstreamManager::add_output_net_id_to_block(const ConfigBlockId& block, - const AtomNetId& output_net_id) { + const std::string& output_net_id) { /* Ensure the input ids are valid */ VTR_ASSERT(true == valid_block_id(block)); diff --git a/openfpga/src/fpga_bitstream/bitstream_manager.h b/libopenfpga/libfpgabitstream/src/bitstream_manager.h similarity index 90% rename from openfpga/src/fpga_bitstream/bitstream_manager.h rename to libopenfpga/libfpgabitstream/src/bitstream_manager.h index 0621a214e..71bd63b43 100644 --- a/openfpga/src/fpga_bitstream/bitstream_manager.h +++ b/libopenfpga/libfpgabitstream/src/bitstream_manager.h @@ -38,9 +38,6 @@ #include #include "vtr_vector.h" -/* Header files from vpr library */ -#include "atom_netlist_fwd.h" - #include "bitstream_manager_fwd.h" /* begin namespace openfpga */ @@ -89,18 +86,28 @@ class BitstreamManager { int block_path_id(const ConfigBlockId& block_id) const; /* Find input net ids of a block */ - std::vector block_input_net_ids(const ConfigBlockId& block_id) const; + std::vector block_input_net_ids(const ConfigBlockId& block_id) const; /* Find input net ids of a block */ - std::vector block_output_net_ids(const ConfigBlockId& block_id) const; + std::vector block_output_net_ids(const ConfigBlockId& block_id) const; public: /* Public Mutators */ /* Add a new configuration bit to the bitstream manager */ ConfigBitId add_bit(const bool& bit_value); + /* Reserve memory for a number of clocks */ + void reserve_blocks(const size_t& num_blocks); + + /* Create a new block of configuration bits */ + ConfigBlockId create_block(); + /* Add a new block of configuration bits to the bitstream manager */ ConfigBlockId add_block(const std::string& block_name); + /* Set a name for a block */ + void set_block_name(const ConfigBlockId& block_id, + const std::string& block_name); + /* Set a block as a child block of another */ void add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block); @@ -111,10 +118,10 @@ class BitstreamManager { void add_path_id_to_block(const ConfigBlockId& block, const int& path_id); /* Add an input net id to a block */ - void add_input_net_id_to_block(const ConfigBlockId& block, const AtomNetId& input_net_id); + void add_input_net_id_to_block(const ConfigBlockId& block, const std::string& input_net_id); /* Add an output net id to a block */ - void add_output_net_id_to_block(const ConfigBlockId& block, const AtomNetId& output_net_id); + void add_output_net_id_to_block(const ConfigBlockId& block, const std::string& output_net_id); /* Add share configuration bits to a configuration bit */ void add_shared_config_bit_values(const ConfigBitId& bit, const std::vector& shared_config_bits); @@ -161,8 +168,8 @@ class BitstreamManager { * -Bitstream manager will NOT check if the id is good for bitstream builders * It just store the results */ - vtr::vector> block_input_net_ids_; - vtr::vector> block_output_net_ids_; + vtr::vector> block_input_net_ids_; + vtr::vector> block_output_net_ids_; /* Unique id of a bit in the Bitstream */ vtr::vector bit_ids_; diff --git a/openfpga/src/fpga_bitstream/bitstream_manager_fwd.h b/libopenfpga/libfpgabitstream/src/bitstream_manager_fwd.h similarity index 100% rename from openfpga/src/fpga_bitstream/bitstream_manager_fwd.h rename to libopenfpga/libfpgabitstream/src/bitstream_manager_fwd.h diff --git a/openfpga/src/fpga_bitstream/bitstream_manager_utils.cpp b/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.cpp similarity index 100% rename from openfpga/src/fpga_bitstream/bitstream_manager_utils.cpp rename to libopenfpga/libfpgabitstream/src/bitstream_manager_utils.cpp diff --git a/openfpga/src/fpga_bitstream/bitstream_manager_utils.h b/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.h similarity index 100% rename from openfpga/src/fpga_bitstream/bitstream_manager_utils.h rename to libopenfpga/libfpgabitstream/src/bitstream_manager_utils.h diff --git a/libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.cpp b/libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.cpp new file mode 100644 index 000000000..e7bcb726c --- /dev/null +++ b/libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.cpp @@ -0,0 +1,181 @@ +/******************************************************************** + * This file includes the top-level function of this library + * which reads an XML of a fabric key to the associated + * data structures + *******************************************************************/ +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "read_xml_util.h" + +#include "openfpga_reserved_words.h" + +#include "read_xml_arch_bitstream.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Parse XML codes of a to an object of BitstreamManager + * This function goes recursively until we reach the leaf node + *******************************************************************/ +static +void rec_read_xml_bitstream_block(pugi::xml_node& xml_bitstream_block, + const pugiutil::loc_data& loc_data, + BitstreamManager& bitstream_manager, + const ConfigBlockId& parent_block) { + + /* Find the name of this bitstream block */ + const std::string& block_name = get_attribute(xml_bitstream_block, "name", loc_data).as_string(); + + /* Create the bitstream block */ + ConfigBlockId curr_block = bitstream_manager.add_block(block_name); + + /* Add it to parent block */ + bitstream_manager.add_child_block(parent_block, curr_block); + + /* Parse input nets if defined */ + pugi::xml_node xml_input_nets = get_single_child(xml_bitstream_block, "input_nets", loc_data, pugiutil::ReqOpt::OPTIONAL); + if (xml_input_nets) { + std::vector input_nets; + size_t num_input_nets = count_children(xml_input_nets, "path", loc_data, pugiutil::ReqOpt::OPTIONAL); + input_nets.resize(num_input_nets); + + /* Find the child paths/nets */ + for (pugi::xml_node xml_input_net : xml_input_nets.children()) { + /* We only care child bitstream blocks here */ + if (xml_input_net.name() != std::string("path")) { + bad_tag(xml_input_net, loc_data, xml_input_nets, {"path"}); + } + const int& id = get_attribute(xml_input_net, "id", loc_data).as_int(); + const std::string& net_name = get_attribute(xml_input_net, "name", loc_data).as_string(); + VTR_ASSERT((size_t)id < input_nets.size()); + input_nets[id] = net_name; + } + + for (const std::string& input_net : input_nets) { + bitstream_manager.add_input_net_id_to_block(curr_block, input_net); + } + } + + /* Parse output nets if defined */ + pugi::xml_node xml_output_nets = get_single_child(xml_bitstream_block, "output_nets", loc_data, pugiutil::ReqOpt::OPTIONAL); + if (xml_output_nets) { + std::vector output_nets; + size_t num_output_nets = count_children(xml_output_nets, "path", loc_data, pugiutil::ReqOpt::OPTIONAL); + output_nets.resize(num_output_nets); + + /* Find the child paths/nets */ + for (pugi::xml_node xml_output_net : xml_output_nets.children()) { + /* We only care child bitstream blocks here */ + if (xml_output_net.name() != std::string("path")) { + bad_tag(xml_output_net, loc_data, xml_output_nets, {"path"}); + } + const int& id = get_attribute(xml_output_net, "id", loc_data).as_int(); + const std::string& net_name = get_attribute(xml_output_net, "name", loc_data).as_string(); + VTR_ASSERT((size_t)id < output_nets.size()); + output_nets[id] = net_name; + } + + for (const std::string& output_net : output_nets) { + bitstream_manager.add_output_net_id_to_block(curr_block, output_net); + } + } + + /* Parse configuration bits */ + pugi::xml_node xml_bitstream = get_single_child(xml_bitstream_block, "bitstream", loc_data, pugiutil::ReqOpt::OPTIONAL); + if (xml_bitstream) { + /* Parse path_id: -2 is an invalid value defined in the bitstream manager internally */ + const int& path_id = get_attribute(xml_bitstream, "path_id", loc_data).as_int(); + if (-2 < path_id) { + bitstream_manager.add_path_id_to_block(curr_block, path_id); + } + + /* Find the child paths/nets */ + for (pugi::xml_node xml_bit : xml_bitstream.children()) { + /* We only care child bitstream blocks here */ + if (xml_bit.name() != std::string("bit")) { + bad_tag(xml_bit, loc_data, xml_bitstream, {"bit"}); + } + const int& bit_value = get_attribute(xml_bit, "value", loc_data).as_int(); + ConfigBitId bit = bitstream_manager.add_bit(1 == bit_value); + /* Link the bit to parent block */ + bitstream_manager.add_bit_to_block(curr_block, bit); + } + } + + /* Go recursively: find all the child blocks and parse */ + for (pugi::xml_node xml_child : xml_bitstream_block.children()) { + /* We only care child bitstream blocks here */ + if (xml_child.name() == std::string("bitstream_block")) { + rec_read_xml_bitstream_block(xml_bitstream_block, loc_data, bitstream_manager, curr_block); + } + } +} + +/******************************************************************** + * Parse XML codes about to an object of Bitstream + *******************************************************************/ +BitstreamManager read_xml_architecture_bitstream(const char* fname) { + + vtr::ScopedStartFinishTimer timer("Read Architecture Bitstream file"); + + BitstreamManager bitstream_manager; + + /* Parse the file */ + pugi::xml_document doc; + pugiutil::loc_data loc_data; + + try { + loc_data = pugiutil::load_xml(doc, fname); + + /* Count the child */ + + pugi::xml_node xml_root = get_single_child(doc, "bitstream_block", loc_data); + + /* Find the name of the top block*/ + const std::string& top_block_name = get_attribute(xml_root, "name", loc_data).as_string(); + + if (top_block_name != std::string(FPGA_TOP_MODULE_NAME)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_root), + "Top-level block must be named as '%s'!\n", + FPGA_TOP_MODULE_NAME); + } + + /* Create the top-level block */ + ConfigBlockId top_block = bitstream_manager.add_block(top_block_name); + + size_t num_blks = count_children(xml_root, "bitstream_block", loc_data, pugiutil::ReqOpt::OPTIONAL); + + /* Reserve bitstream blocks in the data base */ + bitstream_manager.reserve_blocks(num_blks); + + /* Iterate over the children under this node, + * each child should be named after circuit_model + */ + for (pugi::xml_node xml_blk : xml_root.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_blk.name() != std::string("bitstream_block")) { + bad_tag(xml_blk, loc_data, xml_root, {"bitstream_block"}); + } + rec_read_xml_bitstream_block(xml_blk, loc_data, bitstream_manager, top_block); + } + } catch (pugiutil::XmlError& e) { + archfpga_throw(fname, e.line(), + "%s", e.what()); + } + + return bitstream_manager; +} + +} /* end namespace openfpga */ + diff --git a/libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.h b/libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.h new file mode 100644 index 000000000..0f24c802b --- /dev/null +++ b/libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.h @@ -0,0 +1,21 @@ +#ifndef READ_XML_ARCH_BITSTREAM_H +#define READ_XML_ARCH_BITSTREAM_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "pugixml_util.hpp" +#include "pugixml.hpp" +#include "bitstream_manager.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ +/* begin namespace openfpga */ +namespace openfpga { + +BitstreamManager read_xml_architecture_bitstream(const char* fname); + +} /* end namespace openfpga */ + +#endif diff --git a/libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp b/libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp new file mode 100644 index 000000000..05915c1ed --- /dev/null +++ b/libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp @@ -0,0 +1,33 @@ +/******************************************************************** + * Unit test functions to validate the correctness of + * 1. parser of data structures + * 2. writer of data structures + *******************************************************************/ +/* Headers from vtrutils */ +#include "vtr_assert.h" +#include "vtr_log.h" + +/* Headers from fabric key */ +#include "read_xml_arch_bitstream.h" +#include "arch_bitstream_writer.h" + +int main(int argc, const char** argv) { + /* Ensure we have only one or two argument */ + VTR_ASSERT((2 == argc) || (3 == argc)); + + /* Parse the bitstream from an XML file */ + openfpga::BitstreamManager test_bitstream = openfpga::read_xml_architecture_bitstream(argv[1]); + VTR_LOG("Read the bitstream from an XML file: %s.\n", + argv[1]); + + /* Output the circuit library to an XML file + * This is optional only used when there is a second argument + */ + if (3 <= argc) { + openfpga::write_arch_independent_bitstream_to_xml_file(test_bitstream, std::string("fpga_top"), argv[2]); + VTR_LOG("Echo the bitstream to an XML file: %s.\n", + argv[2]); + } +} + + diff --git a/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp b/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp index 00cbbe1e3..edb0bd5cc 100644 --- a/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp +++ b/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp @@ -251,4 +251,20 @@ bool write_space_to_file(std::fstream& fp, return true; } +/******************************************************************** + * Write a number of tab to a file + ********************************************************************/ +bool write_tab_to_file(std::fstream& fp, + const size_t& num_tab) { + if (false == valid_file_stream(fp)) { + return false; + } + + for (size_t i = 0; i < num_tab; ++i) { + fp << "\t"; + } + + return true; +} + } /* namespace openfpga ends */ diff --git a/libopenfpga/libopenfpgautil/src/openfpga_digest.h b/libopenfpga/libopenfpgautil/src/openfpga_digest.h index a28b2c4d0..c1a80ce99 100644 --- a/libopenfpga/libopenfpgautil/src/openfpga_digest.h +++ b/libopenfpga/libopenfpgautil/src/openfpga_digest.h @@ -28,6 +28,9 @@ void create_directory(const std::string& dir_path, const bool& recursive = true) bool write_space_to_file(std::fstream& fp, const size_t& num_space); +bool write_tab_to_file(std::fstream& fp, + const size_t& num_tab); + } /* namespace openfpga ends */ #endif diff --git a/openfpga/src/base/openfpga_reserved_words.h b/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h similarity index 93% rename from openfpga/src/base/openfpga_reserved_words.h rename to libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h index a9b31f64e..e6b89a10b 100644 --- a/openfpga/src/base/openfpga_reserved_words.h +++ b/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h @@ -10,6 +10,11 @@ /* begin namespace openfpga */ namespace openfpga { +/* Top-level module name */ +constexpr char* FPGA_TOP_MODULE_NAME = "fpga_top"; + +constexpr char* CONFIGURABLE_MEMORY_DATA_OUT_NAME = "mem_out"; + /* IO PORT */ /* Prefix of global input, output and inout ports of FPGA fabric */ constexpr char* GIO_INOUT_PREFIX = "gfpga_pad_"; diff --git a/openfpga/CMakeLists.txt b/openfpga/CMakeLists.txt index 7578630af..609602e1a 100644 --- a/openfpga/CMakeLists.txt +++ b/openfpga/CMakeLists.txt @@ -23,6 +23,7 @@ target_link_libraries(libopenfpga libopenfpgashell libopenfpgautil libfabrickey + libfpgabitstream libini libvtrutil libvpr8) diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp index 1a6345040..ea5b0abff 100644 --- a/openfpga/src/base/openfpga_bitstream.cpp +++ b/openfpga/src/base/openfpga_bitstream.cpp @@ -10,6 +10,7 @@ /* Headers from openfpgautil library */ #include "openfpga_digest.h" +#include "openfpga_reserved_words.h" #include "build_device_bitstream.h" #include "arch_bitstream_writer.h" @@ -43,7 +44,7 @@ int fpga_bitstream(OpenfpgaContext& openfpga_ctx, create_directory(src_dir_path); write_arch_independent_bitstream_to_xml_file(openfpga_ctx.bitstream_manager(), - g_vpr_ctx.atom(), + std::string(FPGA_TOP_MODULE_NAME), cmd_context.option_value(cmd, opt_file)); } diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp index 44eb2c8cd..38f20f0ee 100644 --- a/openfpga/src/base/openfpga_naming.cpp +++ b/openfpga/src/base/openfpga_naming.cpp @@ -705,7 +705,7 @@ std::string generate_configuration_chain_tail_name() { * TODO: This could be replaced as a constexpr string *********************************************************************/ std::string generate_configurable_memory_data_out_name() { - return std::string("mem_out"); + return std::string(CONFIGURABLE_MEMORY_DATA_OUT_NAME); } /********************************************************************* @@ -1409,7 +1409,7 @@ std::string generate_fpga_global_io_port_name(const std::string& prefix, * We give a fixed name here, because it is independent from benchmark file ********************************************************************/ std::string generate_fpga_top_module_name() { - return std::string("fpga_top"); + return std::string(FPGA_TOP_MODULE_NAME); } /********************************************************************* @@ -1418,7 +1418,7 @@ std::string generate_fpga_top_module_name() { * We give a fixed name here, because it is independent from benchmark file ********************************************************************/ std::string generate_fpga_top_netlist_name(const std::string& postfix) { - return std::string("fpga_top" + postfix); + return std::string(FPGA_TOP_MODULE_NAME + postfix); } /********************************************************************* diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp index a6e0a6bf3..6d13dfe6f 100644 --- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp @@ -60,6 +60,7 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx, openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), vpr_ctx.device().grid, + vpr_ctx.atom(), openfpga_ctx.vpr_device_annotation(), openfpga_ctx.vpr_clustering_annotation(), openfpga_ctx.vpr_placement_annotation(), diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index fd09e3581..c3de6cbfe 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -128,6 +128,7 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const PhysicalPb& physical_pb, t_pb_graph_pin* des_pb_graph_pin, @@ -221,9 +222,17 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag /* Record path ids, input and output nets */ bitstream_manager.add_path_id_to_block(mux_mem_block, mux_input_pin_id); for (const AtomNetId& input_net : input_nets) { - bitstream_manager.add_input_net_id_to_block(mux_mem_block, input_net); + if (true == atom_ctx.nlist.valid_net_id(input_net)) { + bitstream_manager.add_input_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(input_net)); + } else { + bitstream_manager.add_input_net_id_to_block(mux_mem_block, std::string("unmapped")); + } + } + if (true == atom_ctx.nlist.valid_net_id(output_net)) { + bitstream_manager.add_output_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(output_net)); + } else { + bitstream_manager.add_output_net_id_to_block(mux_mem_block, std::string("unmapped")); } - bitstream_manager.add_output_net_id_to_block(mux_mem_block, output_net); break; } @@ -245,6 +254,7 @@ void build_physical_block_interc_port_bitstream(BitstreamManager& bitstream_mana const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, t_pb_graph_node* physical_pb_graph_node, const PhysicalPb& physical_pb, @@ -256,7 +266,7 @@ void build_physical_block_interc_port_bitstream(BitstreamManager& bitstream_mana for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) { build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block, module_manager, circuit_lib, mux_lib, - device_annotation, + atom_ctx, device_annotation, physical_pb, &(physical_pb_graph_node->input_pins[iport][ipin]), physical_mode); @@ -268,7 +278,7 @@ void build_physical_block_interc_port_bitstream(BitstreamManager& bitstream_mana for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) { build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block, module_manager, circuit_lib, mux_lib, - device_annotation, + atom_ctx, device_annotation, physical_pb, &(physical_pb_graph_node->output_pins[iport][ipin]), physical_mode); @@ -280,7 +290,7 @@ void build_physical_block_interc_port_bitstream(BitstreamManager& bitstream_mana for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) { build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block, module_manager, circuit_lib, mux_lib, - device_annotation, + atom_ctx, device_annotation, physical_pb, &(physical_pb_graph_node->clock_pins[iport][ipin]), physical_mode); @@ -305,6 +315,7 @@ void build_physical_block_interc_bitstream(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, t_pb_graph_node* physical_pb_graph_node, const PhysicalPb& physical_pb, @@ -327,7 +338,7 @@ void build_physical_block_interc_bitstream(BitstreamManager& bitstream_manager, */ build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block, module_manager, circuit_lib, mux_lib, - device_annotation, + atom_ctx, device_annotation, physical_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_OUTPUT, physical_mode); @@ -346,13 +357,13 @@ void build_physical_block_interc_bitstream(BitstreamManager& bitstream_manager, /* For each child_pb_graph_node input pins*/ build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block, module_manager, circuit_lib, mux_lib, - device_annotation, + atom_ctx, device_annotation, child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_INPUT, physical_mode); /* For clock pins, we should do the same work */ build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block, module_manager, circuit_lib, mux_lib, - device_annotation, + atom_ctx, device_annotation, child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_CLOCK, physical_mode); } @@ -478,6 +489,7 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const e_side& border_side, const PhysicalPb& physical_pb, @@ -508,6 +520,7 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager, /* Go recursively */ rec_build_physical_block_bitstream(bitstream_manager, pb_configurable_block, module_manager, circuit_lib, mux_lib, + atom_ctx, device_annotation, border_side, physical_pb, child_pb, @@ -552,6 +565,7 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager, /* Generate the bitstream for the interconnection in this physical block */ build_physical_block_interc_bitstream(bitstream_manager, pb_configurable_block, module_manager, circuit_lib, mux_lib, + atom_ctx, device_annotation, physical_pb_graph_node, physical_pb, physical_mode); @@ -569,6 +583,7 @@ void build_physical_block_bitstream(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, @@ -603,6 +618,7 @@ void build_physical_block_bitstream(BitstreamManager& bitstream_manager, /* Recursively traverse the pb_graph and generate bitstream */ rec_build_physical_block_bitstream(bitstream_manager, grid_configurable_block, module_manager, circuit_lib, mux_lib, + atom_ctx, device_annotation, border_side, PhysicalPb(), PhysicalPbId::INVALID(), lb_type->pb_graph_head, z); @@ -617,6 +633,7 @@ void build_physical_block_bitstream(BitstreamManager& bitstream_manager, /* Recursively traverse the pb_graph and generate bitstream */ rec_build_physical_block_bitstream(bitstream_manager, grid_configurable_block, module_manager, circuit_lib, mux_lib, + atom_ctx, device_annotation, border_side, phy_pb, top_pb_id, pb_graph_head, z); } @@ -637,6 +654,7 @@ void build_grid_bitstream(BitstreamManager& bitstream_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const DeviceGrid& grids, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, @@ -662,6 +680,7 @@ void build_grid_bitstream(BitstreamManager& bitstream_manager, vtr::Point grid_coord(ix, iy); build_physical_block_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, + atom_ctx, device_annotation, cluster_annotation, place_annotation, grids, grid_coord, NUM_SIDES); @@ -709,6 +728,7 @@ void build_grid_bitstream(BitstreamManager& bitstream_manager, } build_physical_block_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, + atom_ctx, device_annotation, cluster_annotation, place_annotation, grids, io_coordinate, io_side); diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.h b/openfpga/src/fpga_bitstream/build_grid_bitstream.h index 6f192a9b7..be2425c5a 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.h +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.h @@ -5,6 +5,7 @@ * Include header files that are required by function declaration *******************************************************************/ #include +#include "vpr_context.h" #include "device_grid.h" #include "bitstream_manager.h" #include "module_manager.h" @@ -27,6 +28,7 @@ void build_grid_bitstream(BitstreamManager& bitstream_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const DeviceGrid& grids, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp index b396385a0..457b1d004 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp @@ -107,10 +107,18 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager, bitstream_manager.add_path_id_to_block(mux_mem_block, path_id); for (const ClusterNetId& input_net : input_nets) { AtomNetId input_atom_net = atom_ctx.lookup.atom_net(input_net); - bitstream_manager.add_input_net_id_to_block(mux_mem_block, input_atom_net); + if (true == atom_ctx.nlist.valid_net_id(input_atom_net)) { + bitstream_manager.add_input_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(input_atom_net)); + } else { + bitstream_manager.add_input_net_id_to_block(mux_mem_block, std::string("unmapped")); + } } AtomNetId output_atom_net = atom_ctx.lookup.atom_net(output_net); - bitstream_manager.add_output_net_id_to_block(mux_mem_block, output_atom_net); + if (true == atom_ctx.nlist.valid_net_id(output_atom_net)) { + bitstream_manager.add_output_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(output_atom_net)); + } else { + bitstream_manager.add_output_net_id_to_block(mux_mem_block, std::string("unmapped")); + } } /******************************************************************** @@ -290,13 +298,20 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager, bitstream_manager.add_path_id_to_block(mux_mem_block, path_id); for (const ClusterNetId& input_net : input_nets) { AtomNetId input_atom_net = atom_ctx.lookup.atom_net(input_net); - bitstream_manager.add_input_net_id_to_block(mux_mem_block, input_atom_net); + if (true == atom_ctx.nlist.valid_net_id(input_atom_net)) { + bitstream_manager.add_input_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(input_atom_net)); + } else { + bitstream_manager.add_input_net_id_to_block(mux_mem_block, std::string("unmapped")); + } } AtomNetId output_atom_net = atom_ctx.lookup.atom_net(output_net); - bitstream_manager.add_output_net_id_to_block(mux_mem_block, output_atom_net); + if (true == atom_ctx.nlist.valid_net_id(output_atom_net)) { + bitstream_manager.add_output_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(output_atom_net)); + } else { + bitstream_manager.add_output_net_id_to_block(mux_mem_block, std::string("unmapped")); + } } - /******************************************************************** * This function generates bitstream for an interconnection, * i.e., a routing multiplexer, in a Connection Block From 1e763515b3ba64300016da5e2b100f13b546cb07 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 20 Jun 2020 18:39:21 -0600 Subject: [PATCH 28/35] bug fix in bitstream parser and writer --- .../libfpgabitstream/src/arch_bitstream_writer.cpp | 4 ++-- .../libfpgabitstream/src/read_xml_arch_bitstream.cpp | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp b/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp index ebb0a3129..2e4e81054 100644 --- a/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp +++ b/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp @@ -98,7 +98,7 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp, for (const std::string& net : bitstream_manager.block_input_net_ids(block)) { write_tab_to_file(fp, hierarchy_level + 2); fp << ""; @@ -116,7 +116,7 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp, for (const std::string& net : bitstream_manager.block_output_net_ids(block)) { write_tab_to_file(fp, hierarchy_level + 2); fp << ""; diff --git a/libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.cpp b/libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.cpp index e7bcb726c..3895b85b6 100644 --- a/libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.cpp +++ b/libopenfpga/libfpgabitstream/src/read_xml_arch_bitstream.cpp @@ -57,7 +57,7 @@ void rec_read_xml_bitstream_block(pugi::xml_node& xml_bitstream_block, bad_tag(xml_input_net, loc_data, xml_input_nets, {"path"}); } const int& id = get_attribute(xml_input_net, "id", loc_data).as_int(); - const std::string& net_name = get_attribute(xml_input_net, "name", loc_data).as_string(); + const std::string& net_name = get_attribute(xml_input_net, "net_name", loc_data).as_string(); VTR_ASSERT((size_t)id < input_nets.size()); input_nets[id] = net_name; } @@ -81,7 +81,7 @@ void rec_read_xml_bitstream_block(pugi::xml_node& xml_bitstream_block, bad_tag(xml_output_net, loc_data, xml_output_nets, {"path"}); } const int& id = get_attribute(xml_output_net, "id", loc_data).as_int(); - const std::string& net_name = get_attribute(xml_output_net, "name", loc_data).as_string(); + const std::string& net_name = get_attribute(xml_output_net, "net_name", loc_data).as_string(); VTR_ASSERT((size_t)id < output_nets.size()); output_nets[id] = net_name; } @@ -95,7 +95,7 @@ void rec_read_xml_bitstream_block(pugi::xml_node& xml_bitstream_block, pugi::xml_node xml_bitstream = get_single_child(xml_bitstream_block, "bitstream", loc_data, pugiutil::ReqOpt::OPTIONAL); if (xml_bitstream) { /* Parse path_id: -2 is an invalid value defined in the bitstream manager internally */ - const int& path_id = get_attribute(xml_bitstream, "path_id", loc_data).as_int(); + const int& path_id = get_attribute(xml_bitstream, "path_id", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-2); if (-2 < path_id) { bitstream_manager.add_path_id_to_block(curr_block, path_id); } @@ -117,7 +117,7 @@ void rec_read_xml_bitstream_block(pugi::xml_node& xml_bitstream_block, for (pugi::xml_node xml_child : xml_bitstream_block.children()) { /* We only care child bitstream blocks here */ if (xml_child.name() == std::string("bitstream_block")) { - rec_read_xml_bitstream_block(xml_bitstream_block, loc_data, bitstream_manager, curr_block); + rec_read_xml_bitstream_block(xml_child, loc_data, bitstream_manager, curr_block); } } } From d526f0878289fe74fdbf88b7c006ed92929ddfa7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 20 Jun 2020 18:48:19 -0600 Subject: [PATCH 29/35] deploy bitstream reader in openfpga shell --- openfpga/src/base/openfpga_bitstream.cpp | 24 ++++++++++++------- .../src/base/openfpga_bitstream_command.cpp | 12 ++++++---- ...onfiguration_chain_example_script.openfpga | 2 +- ...uplicated_grid_pin_example_script.openfpga | 2 +- .../example_script.openfpga | 2 +- ...fast_configuration_example_script.openfpga | 2 +- .../flatten_routing_example_script.openfpga | 2 +- .../full_testbench_example_script.openfpga | 2 +- ...rate_secure_fabric_example_script.openfpga | 2 +- ...re_fabric_from_key_example_script.openfpga | 2 +- ...generate_testbench_example_script.openfpga | 2 +- .../implicit_verilog_example_script.openfpga | 2 +- .../mcnc_example_script.openfpga | 2 +- .../sdc_time_unit_example_script.openfpga | 2 +- 14 files changed, 36 insertions(+), 24 deletions(-) diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp index ea5b0abff..870b5935a 100644 --- a/openfpga/src/base/openfpga_bitstream.cpp +++ b/openfpga/src/base/openfpga_bitstream.cpp @@ -12,8 +12,11 @@ #include "openfpga_digest.h" #include "openfpga_reserved_words.h" -#include "build_device_bitstream.h" +/* Headers from fpgabitstream library */ +#include "read_xml_arch_bitstream.h" #include "arch_bitstream_writer.h" + +#include "build_device_bitstream.h" #include "fabric_bitstream_writer.h" #include "build_fabric_bitstream.h" #include "openfpga_bitstream.h" @@ -31,21 +34,26 @@ int fpga_bitstream(OpenfpgaContext& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); - CommandOptionId opt_file = cmd.option("file"); + CommandOptionId opt_write_file = cmd.option("write_file"); + CommandOptionId opt_read_file = cmd.option("read_file"); - openfpga_ctx.mutable_bitstream_manager() = build_device_bitstream(g_vpr_ctx, - openfpga_ctx, - cmd_context.option_enable(cmd, opt_verbose)); + if (true == cmd_context.option_enable(cmd, opt_read_file)) { + openfpga_ctx.mutable_bitstream_manager() = read_xml_architecture_bitstream(cmd_context.option_value(cmd, opt_write_file).c_str()); + } else { + openfpga_ctx.mutable_bitstream_manager() = build_device_bitstream(g_vpr_ctx, + openfpga_ctx, + cmd_context.option_enable(cmd, opt_verbose)); + } - if (true == cmd_context.option_enable(cmd, opt_file)) { - std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file)); + if (true == cmd_context.option_enable(cmd, opt_write_file)) { + std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_write_file)); /* Create directories */ create_directory(src_dir_path); write_arch_independent_bitstream_to_xml_file(openfpga_ctx.bitstream_manager(), std::string(FPGA_TOP_MODULE_NAME), - cmd_context.option_value(cmd, opt_file)); + cmd_context.option_value(cmd, opt_write_file)); } /* TODO: should identify the error code from internal function execution */ diff --git a/openfpga/src/base/openfpga_bitstream_command.cpp b/openfpga/src/base/openfpga_bitstream_command.cpp index 70149dd43..1a337e9d0 100644 --- a/openfpga/src/base/openfpga_bitstream_command.cpp +++ b/openfpga/src/base/openfpga_bitstream_command.cpp @@ -46,10 +46,14 @@ ShellCommandId add_openfpga_arch_bitstream_command(openfpga::Shell& dependent_cmds) { Command shell_cmd("build_architecture_bitstream"); - /* Add an option '--file' in short '-f'*/ - CommandOptionId opt_file = shell_cmd.add_option("file", true, "file path to output the bitstream database"); - shell_cmd.set_option_short_name(opt_file, "f"); - shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + /* Add an option '--write_file' */ + CommandOptionId opt_write_file = shell_cmd.add_option("write_file", false, "file path to output the bitstream database"); + shell_cmd.set_option_require_value(opt_write_file, openfpga::OPT_STRING); + + /* Add an option '--read_file' */ + CommandOptionId opt_read_file = shell_cmd.add_option("read_file", false, "file path to read the bitstream database"); + shell_cmd.set_option_require_value(opt_read_file, openfpga::OPT_STRING); + /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Enable verbose output"); diff --git a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga index 0cf8a6448..33891b72d 100644 --- a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga @@ -37,7 +37,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga index ae729290e..97f540116 100644 --- a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga @@ -37,7 +37,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga index ae729290e..97f540116 100644 --- a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga @@ -37,7 +37,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga index fceabcaaa..d6800e2f1 100644 --- a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga @@ -37,7 +37,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga index 5ab1c56b6..e5cb63413 100644 --- a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga @@ -37,7 +37,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga index ae729290e..97f540116 100644 --- a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga @@ -37,7 +37,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga index 4f340704b..d98e9b74d 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga @@ -40,7 +40,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga index a61336d61..47b3edce3 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga @@ -40,7 +40,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga index 971f8d374..a0e09687f 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga @@ -37,7 +37,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga index e86ba055e..ed7ccf1de 100644 --- a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga @@ -37,7 +37,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga index 5f17a5c65..6c753df2f 100644 --- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga @@ -37,7 +37,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose diff --git a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga index 36c3c88b9..fc8d333f5 100644 --- a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga @@ -37,7 +37,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose From 8b8d92d186b2c10c133626f40aaad81e35be3c73 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 20 Jun 2020 18:59:45 -0600 Subject: [PATCH 30/35] update documentation for new bitstream file format --- .../fpga_bitstream/generic_bitstream.rst | 120 ++++++++++-------- .../fpga_bitstream_commands.rst | 4 +- 2 files changed, 73 insertions(+), 51 deletions(-) diff --git a/docs/source/manual/fpga_bitstream/generic_bitstream.rst b/docs/source/manual/fpga_bitstream/generic_bitstream.rst index 7d4bebffa..a434096bc 100644 --- a/docs/source/manual/fpga_bitstream/generic_bitstream.rst +++ b/docs/source/manual/fpga_bitstream/generic_bitstream.rst @@ -11,14 +11,17 @@ This can be regarded as a raw bitstream used for - ``an exchangeable file format for bitstream assembler``: Software engineers can use the raw bitstream to build a bitstream assembler which organize the bitstream in the loadable formate to FPGA chips. - - ``creation of artificial bitstream``: Test engineers can craft artificial bitstreams to test each element of the FPGA fabric, which is typically not synthesizable by VPR. + - ``creation of artificial bitstream``: Test engineers can craft artificial bitstreams to test each element of the FPGA fabric, which is typically not synthesizable by VPR. Use the ``--read_file`` option to load the artifical bitsteam to OpenFPGA (see details in :ref:`openfpga_bitstream_commands`). .. warning:: The fabric-independent bitstream cannot be directly loaded to FPGA fabrics File Format ``````````` -OpenFPGA can output the generic bitstream to an XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes the follwoing information: +OpenFPGA can output the generic bitstream to an XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes the following information: + - ``name`` represents the instance name which you can find in the fabric netlists + + - ``hierarchy_level`` represents the depth of this block in the hierarchy of the FPGA fabric. It always starts from 0 as the root. - ``hierarchy`` represents the location of this block in FPGA fabric. The hierachy includes the full hierarchy of this block @@ -27,9 +30,9 @@ OpenFPGA can output the generic bitstream to an XML format, which is easy to deb - ``level`` denotes the depth of the block in the hierarchy - - ``input_nets`` represents the net names that are mapped to the inputs of block. Unused inputs will be tagged as ``unmapped`` which is a reserved word of OpenFPGA. + - ``input_nets`` represents the path ids and net names that are mapped to the inputs of block. Unused inputs will be tagged as ``unmapped`` which is a reserved word of OpenFPGA. Path id corresponds the selected ``path_id`` in the ```` node. - - ``output_nets`` represents the net names that are mapped to the outputs of block. Unused outputs will be tagged as ``unmapped`` which is a reserved word OpenFPGA. + - ``output_nets`` represents the path ids and net names that are mapped to the outputs of block. Unused outputs will be tagged as ``unmapped`` which is a reserved word OpenFPGA. - ``bitstream`` represents the configuration bits affiliated to this block. @@ -43,52 +46,69 @@ OpenFPGA can output the generic bitstream to an XML format, which is easy to deb .. code-block:: xml - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - + + + + + + + + + + + + - - - - - - - - - - - - - - - + + + - - - - - - - - - - - - SAP_out[1] SAP_out[1] - - - SAP_out[1] - - - - - - - diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst index 62ab8bec4..731f99f94 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst @@ -17,7 +17,9 @@ build_architecture_bitstream Decode VPR implementing results to an fabric-independent bitstream database - - ``--file`` or ``-f`` Output the fabric-independent bitstream to an XML file + - ``--read_file`` Read the fabric-independent bitstream from an XML file. When this is enabled, bitstream generation will NOT consider VPR results. + + - ``--write_file`` Output the fabric-independent bitstream to an XML file - ``--verbose`` Show verbose log From 3bcdd0e1d446f5b4bd1811302e0e64d910568ddf Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 20 Jun 2020 19:01:33 -0600 Subject: [PATCH 31/35] clean up writer format for bitstream --- libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp b/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp index 2e4e81054..17a3bc9cf 100644 --- a/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp +++ b/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp @@ -101,10 +101,10 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp, fp << " net_name=\""; fp << net; fp << "\"/>"; + fp << "\n"; path_counter++; } - fp << "\n"; write_tab_to_file(fp, hierarchy_level + 1); fp << "\n"; } @@ -119,10 +119,10 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp, fp << " net_name=\""; fp << net; fp << "\"/>"; + fp << "\n"; path_counter++; } - fp << "\n"; write_tab_to_file(fp, hierarchy_level + 1); fp << "\n"; } From 2f33c35a4f500a47c213701c835ae2c174ce7da8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 20 Jun 2020 19:05:44 -0600 Subject: [PATCH 32/35] add example XML file for bitstream --- .../arch_bitstream_example.xml | 8026 +++++++++++++++++ 1 file changed, 8026 insertions(+) create mode 100644 libopenfpga/libfpgabitstream/bitstream_example/arch_bitstream_example.xml diff --git a/libopenfpga/libfpgabitstream/bitstream_example/arch_bitstream_example.xml b/libopenfpga/libfpgabitstream/bitstream_example/arch_bitstream_example.xml new file mode 100644 index 000000000..4d1c1a7e0 --- /dev/null +++ b/libopenfpga/libfpgabitstream/bitstream_example/arch_bitstream_example.xml @@ -0,0 +1,8026 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + 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aded675633b4f2c3fe84f1d3034ca6ae4e4c95df Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 21 Jun 2020 13:06:39 -0600 Subject: [PATCH 33/35] rename files in fpga bitstream library to be consistent with conventions --- ...tstream_writer.cpp => write_xml_arch_bitstream.cpp} | 10 ++++------ ...h_bitstream_writer.h => write_xml_arch_bitstream.h} | 9 ++++----- .../libfpgabitstream/test/test_arch_bitstream.cpp | 4 ++-- openfpga/src/base/openfpga_bitstream.cpp | 8 +++----- 4 files changed, 13 insertions(+), 18 deletions(-) rename libopenfpga/libfpgabitstream/src/{arch_bitstream_writer.cpp => write_xml_arch_bitstream.cpp} (94%) rename libopenfpga/libfpgabitstream/src/{arch_bitstream_writer.h => write_xml_arch_bitstream.h} (61%) diff --git a/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp b/libopenfpga/libfpgabitstream/src/write_xml_arch_bitstream.cpp similarity index 94% rename from libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp rename to libopenfpga/libfpgabitstream/src/write_xml_arch_bitstream.cpp index 17a3bc9cf..0cc8c88b0 100644 --- a/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.cpp +++ b/libopenfpga/libfpgabitstream/src/write_xml_arch_bitstream.cpp @@ -17,7 +17,7 @@ #include "openfpga_reserved_words.h" #include "bitstream_manager_utils.h" -#include "arch_bitstream_writer.h" +#include "write_xml_arch_bitstream.h" /* begin namespace openfpga */ namespace openfpga { @@ -166,9 +166,8 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp, * specific FPGAs * 3. TODO: support FASM format *******************************************************************/ -void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstream_manager, - const std::string& top_block_name, - const std::string& fname) { +void write_xml_architecture_bitstream(const BitstreamManager& bitstream_manager, + const std::string& fname) { /* Ensure that we have a valid file name */ if (true == fname.empty()) { VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n"); @@ -188,9 +187,8 @@ void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstr /* Find the top block, which has not parents */ std::vector top_block = find_bitstream_manager_top_blocks(bitstream_manager); - /* Make sure we have only 1 top block and its name matches the top module */ + /* Make sure we have only 1 top block */ VTR_ASSERT(1 == top_block.size()); - VTR_ASSERT(0 == top_block_name.compare(bitstream_manager.block_name(top_block[0]))); /* Write bitstream, block by block, in a recursive way */ rec_write_block_bitstream_to_xml_file(fp, bitstream_manager, top_block[0], 0); diff --git a/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.h b/libopenfpga/libfpgabitstream/src/write_xml_arch_bitstream.h similarity index 61% rename from libopenfpga/libfpgabitstream/src/arch_bitstream_writer.h rename to libopenfpga/libfpgabitstream/src/write_xml_arch_bitstream.h index 91f9e271d..5d30b8d6d 100644 --- a/libopenfpga/libfpgabitstream/src/arch_bitstream_writer.h +++ b/libopenfpga/libfpgabitstream/src/write_xml_arch_bitstream.h @@ -1,5 +1,5 @@ -#ifndef ARCH_BITSTREAM_WRITER_H -#define ARCH_BITSTREAM_WRITER_H +#ifndef WRITE_XML_ARCH_BITSTREAM_H +#define WRITE_XML_ARCH_BITSTREAM_H /******************************************************************** * Include header files that are required by function declaration @@ -14,9 +14,8 @@ /* begin namespace openfpga */ namespace openfpga { -void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstream_manager, - const std::string& top_block_name, - const std::string& fname); +void write_xml_architecture_bitstream(const BitstreamManager& bitstream_manager, + const std::string& fname); } /* end namespace openfpga */ diff --git a/libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp b/libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp index 05915c1ed..88d00601e 100644 --- a/libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp +++ b/libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp @@ -9,7 +9,7 @@ /* Headers from fabric key */ #include "read_xml_arch_bitstream.h" -#include "arch_bitstream_writer.h" +#include "write_xml_arch_bitstream.h" int main(int argc, const char** argv) { /* Ensure we have only one or two argument */ @@ -24,7 +24,7 @@ int main(int argc, const char** argv) { * This is optional only used when there is a second argument */ if (3 <= argc) { - openfpga::write_arch_independent_bitstream_to_xml_file(test_bitstream, std::string("fpga_top"), argv[2]); + openfpga::write_xml_architecture_bitstream(test_bitstream, argv[2]); VTR_LOG("Echo the bitstream to an XML file: %s.\n", argv[2]); } diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp index 870b5935a..32fb8b945 100644 --- a/openfpga/src/base/openfpga_bitstream.cpp +++ b/openfpga/src/base/openfpga_bitstream.cpp @@ -10,11 +10,10 @@ /* Headers from openfpgautil library */ #include "openfpga_digest.h" -#include "openfpga_reserved_words.h" /* Headers from fpgabitstream library */ #include "read_xml_arch_bitstream.h" -#include "arch_bitstream_writer.h" +#include "write_xml_arch_bitstream.h" #include "build_device_bitstream.h" #include "fabric_bitstream_writer.h" @@ -51,9 +50,8 @@ int fpga_bitstream(OpenfpgaContext& openfpga_ctx, /* Create directories */ create_directory(src_dir_path); - write_arch_independent_bitstream_to_xml_file(openfpga_ctx.bitstream_manager(), - std::string(FPGA_TOP_MODULE_NAME), - cmd_context.option_value(cmd, opt_write_file)); + write_xml_architecture_bitstream(openfpga_ctx.bitstream_manager(), + cmd_context.option_value(cmd, opt_write_file)); } /* TODO: should identify the error code from internal function execution */ From 161d1474c1da68070d75da5bee45e302b32b84fb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 24 Jun 2020 10:36:08 -0600 Subject: [PATCH 34/35] keep tutorial updated to the latest regression test organization --- .../design_flow/blif_to_verification.rst | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/docs/source/tutorials/design_flow/blif_to_verification.rst b/docs/source/tutorials/design_flow/blif_to_verification.rst index d3b27a43f..26a0b87cf 100644 --- a/docs/source/tutorials/design_flow/blif_to_verification.rst +++ b/docs/source/tutorials/design_flow/blif_to_verification.rst @@ -18,9 +18,9 @@ We will simply execute the following openfpga task-run by .. code-block:: shell - python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain + python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_chain -Detailed settings, such as architecture XML files and RTL designs, can be found at ``${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf``. +Detailed settings, such as architecture XML files and RTL designs, can be found at ``${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/config/task.conf``. .. note:: ``${OPENFPGA_PATH}`` is the root directory of OpenFPGA @@ -28,7 +28,7 @@ After this task-run, you can find all the generated netlists and testbenches at .. code-block:: shell - ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/ + ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/ .. note:: See :ref:`fabric_netlists` and :ref:`fpga_verilog_testbench` for the netlist details. @@ -43,7 +43,7 @@ The simulation results are logged in .. code-block:: shell - ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/vvp_sim_output.txt + ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/vvp_sim_output.txt If the verification passed, you should be able to see ``Simulation Succeed`` in the log file. @@ -53,7 +53,7 @@ To visualize the waveforms, you can use the `GTKWave .. code-block:: shell - gtkwave ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd & + gtkwave ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd & Manual Method ^^^^^^^^^^^^^ @@ -62,7 +62,7 @@ If you want to run iVerilog simulation manually, you can follow these steps: .. code-block:: shell - cd ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH + cd ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH source iverilog_output.txt @@ -73,9 +73,9 @@ Debugging Tips If you want to apply full visibility to the signals, you need to change the following line in - .. code-block:: shell +.. code-block:: shell - ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/and2_autocheck_top_tb.v + ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/and2_autocheck_top_tb.v from @@ -100,13 +100,13 @@ You can simply call the python script in the following line: .. code-block:: shell - python3 openfpga_flow/scripts/run_modelsim.py openfpga_shell/configuration_chain --run_sim + python3 openfpga_flow/scripts/run_modelsim.py openfpga_shell/full_testbench/configuration_chain --run_sim The script will automatically create a Modelsim project at .. code-block:: shell - ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/MSIM2/ + ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/MSIM2/ and run the simulation. @@ -119,7 +119,7 @@ Modify the ``fpga_defines.v`` (see details in :ref:`fabric_netlists`) at .. code-block:: shell - ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/ + ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shellfull_testbench//configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/ by **deleting** the line @@ -131,7 +131,7 @@ Create a folder ``MSIM`` under .. code-block:: shell - ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/ + ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/ Under the ``MSIM`` folder, create symbolic links to ``SRC`` folder and reference benchmarks by @@ -149,7 +149,7 @@ Add the following file to your project: .. code-block:: shell - ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/and2_include_netlists.v + ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/and2_include_netlists.v Compile the netlists, create a simulation configuration and specify ``and2_autocheck_top_tb`` at the top unit. From db5397fa75b51de973111c41f38c9fc1730e09d7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 24 Jun 2020 10:51:26 -0600 Subject: [PATCH 35/35] update tutorial about architecture to synchronize with latest file organization --- .../tutorials/arch_modeling/quick_start.rst | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/docs/source/tutorials/arch_modeling/quick_start.rst b/docs/source/tutorials/arch_modeling/quick_start.rst index 0efbddf0d..1b31300d1 100644 --- a/docs/source/tutorials/arch_modeling/quick_start.rst +++ b/docs/source/tutorials/arch_modeling/quick_start.rst @@ -4,8 +4,9 @@ A Quick Start ------------- In this tutorial, we will consider a simple but representative FPGA architecture to show you how to - - Adapt the VPR architecture XML file to OpenFPGA acceptable format - - Create the OpenFPGA architecture XMl file to customize the primitive circuits + - Adapt a VPR architecture XML file to OpenFPGA acceptable format + - Create an OpenFPGA architecture XML file to customize the primitive circuits + - Create a simulation setting XML file to specify the simulation settings Through this quick example, we will introduce the key steps to build your own FPGA based on a VPR architecture template. @@ -128,6 +129,7 @@ Craft OpenFPGA Architecture OpenFPGA needs another XML file which contains detailed modeling on the physical design of FPGA architecture. This is designed to minimize the modification on the original VPR architecture file, so that it can be reused. +You may create an XML file `k4_n4_openfpga_arch.xml` and then add contents shown as follows. Overview on the Structure ^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -136,7 +138,6 @@ An OpenFPGA architecture including the following parts. - Architecture modeling with a focus on circuit-level description - Configuration protocol definition - Annotation on the VPR architecture modules - - Simulation settings These parts are organized as follows in the XML file. @@ -173,10 +174,6 @@ These parts are organized as follows in the XML file. - - ... - - Technology Library Definition ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Technology information are all stored under the ```` node, which contains transistor-level information to build the FPGA. @@ -474,10 +471,13 @@ The complete annotation is shown as follows: See details in :ref:`annotate_vpr_arch`. Simulation Settings -^^^^^^^^^^^^^^^^^^^ +~~~~~~~~~~~~~~~~~~~ +OpenFPGA needs an XML file where detailed simulation settings are defined. The simulation settings contain critical parameters to build testbenches for verify the FPGA fabric. +You may create an XML file `k4_n4_openfpga_simulation.xml` and then add contents shown as follows. + The complete annotation is shown as follows: .. code-block:: xml