diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
index 1276e8071..a22bd9818 100755
--- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh
+++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
@@ -239,6 +239,7 @@ run-task basic_tests/global_tile_ports/global_tile_4clock_pin $@
echo -e "Testing programmable clock architecture";
run-task basic_tests/clock_network/homo_1clock_1reset_1layer_2entry $@
run-task basic_tests/clock_network/homo_1clock_2layer $@
+run-task basic_tests/clock_network/homo_1clock_2layer_dec $@
run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@
run-task basic_tests/clock_network/homo_2clock_2layer $@
run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/clk_arch_1clk_1rst_2layer.xml
new file mode 100644
index 000000000..89f030970
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/clk_arch_1clk_1rst_2layer.xml
@@ -0,0 +1,32 @@
+
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diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_reset.xml
new file mode 100644
index 000000000..3788a1411
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_reset.xml
@@ -0,0 +1,8 @@
+
+
+
+
+
+
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_resetb.xml
new file mode 100644
index 000000000..1311926f5
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_resetb.xml
@@ -0,0 +1,8 @@
+
+
+
+
+
+
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/repack_pin_constraints.xml
new file mode 100644
index 000000000..06a125111
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/repack_pin_constraints.xml
@@ -0,0 +1,4 @@
+
+
+
+
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/task.conf
new file mode 100644
index 000000000..014465ced
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/task.conf
@@ -0,0 +1,54 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 3*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=32
+openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml
+openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
+openfpga_route_clock_options=
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
+bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = counter
+bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
+bench0_openfpga_verilog_testbench_port_mapping=
+
+bench1_top = counter
+bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml
+bench1_openfpga_verilog_testbench_port_mapping=
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml
new file mode 100644
index 000000000..111b5709d
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml
@@ -0,0 +1,642 @@
+
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+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
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+ clb.reset clb.clk
+
+ clb.O[0:3] clb.I[0:5]
+ clb.O[4:7] clb.I[6:11]
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