diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp
index 6fe98875c..d118c38f1 100644
--- a/openfpga/src/annotation/append_clock_rr_graph.cpp
+++ b/openfpga/src/annotation/append_clock_rr_graph.cpp
@@ -753,7 +753,8 @@ static int add_rr_graph_opin2clk_intermediate_edges(
       VTR_LOGV(verbose, "Finding internal drivers on spine '%s'...\n",
                clk_ntwk.spine_name(ispine).c_str());
       for (auto ipin : clk_ntwk.pins(clk_tree)) {
-        for (const vtr::Point<int>& coord : clk_ntwk.spine_coordinates(ispine)) {
+        for (const vtr::Point<int>& coord :
+             clk_ntwk.spine_coordinates(ispine)) {
           if (clk_ntwk.spine_intermediate_drivers(ispine, coord).empty()) {
             continue;
           }
@@ -762,13 +763,16 @@ static int add_rr_graph_opin2clk_intermediate_edges(
           Direction des_spine_direction = clk_ntwk.spine_direction(ispine);
           ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine);
           vtr::Point<int> des_coord(coord.x(), coord.y());
-          /* des node depends on the type of routing track and direction. But it should be a starting point at the current SB[x][y] */
-          if (des_spine_direction == Direction::INC && clk_ntwk.spine_track_type(ispine) == CHANX) {
+          /* des node depends on the type of routing track and direction. But it
+           * should be a starting point at the current SB[x][y] */
+          if (des_spine_direction == Direction::INC &&
+              clk_ntwk.spine_track_type(ispine) == CHANX) {
             des_coord.set_x(coord.x() + 1);
-          } 
-          if (des_spine_direction == Direction::INC && clk_ntwk.spine_track_type(ispine) == CHANY) {
+          }
+          if (des_spine_direction == Direction::INC &&
+              clk_ntwk.spine_track_type(ispine) == CHANY) {
             des_coord.set_y(coord.y() + 1);
-          } 
+          }
           RRNodeId des_node = clk_rr_lookup.find_node(
             des_coord.x(), des_coord.y(), clk_tree, des_spine_level, ipin,
             des_spine_direction, verbose);
@@ -776,7 +780,8 @@ static int add_rr_graph_opin2clk_intermediate_edges(
             continue;
           }
           /* Walk through each qualified OPIN, build edges */
-          std::vector<ClockInternalDriverId> int_driver_ids = clk_ntwk.spine_intermediate_drivers(ispine, coord);
+          std::vector<ClockInternalDriverId> int_driver_ids =
+            clk_ntwk.spine_intermediate_drivers(ispine, coord);
           for (RRNodeId src_node : find_clock_opin2track_node(
                  grids, rr_graph_view, layer, coord, clk_ntwk, ipin,
                  int_driver_ids, verbose)) {
@@ -786,7 +791,9 @@ static int add_rr_graph_opin2clk_intermediate_edges(
               src_node, des_node, clk_ntwk.default_driver_switch(), false);
             edge_count++;
           }
-          VTR_LOGV(verbose, "\tWill add %lu edges from OPINs as intermediate drivers at (x=%lu, y=%lu)\n",
+          VTR_LOGV(verbose,
+                   "\tWill add %lu edges from OPINs as intermediate drivers at "
+                   "(x=%lu, y=%lu)\n",
                    edge_count - curr_edge_count, des_coord.x(), des_coord.y());
         }
       }
@@ -798,7 +805,6 @@ static int add_rr_graph_opin2clk_intermediate_edges(
   return CMD_EXEC_SUCCESS;
 }
 
-
 /********************************************************************
  * Add edges to interconnect clock nodes
  * Walk through the routing tracks in each connection block (driver nodes)
@@ -875,9 +881,9 @@ static void add_rr_graph_clock_edges(
   add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create,
                               clk_rr_lookup, rr_graph_view, grids, layer,
                               clk_ntwk, verbose);
-  add_rr_graph_opin2clk_intermediate_edges(rr_graph_builder, num_edges_to_create,
-                              clk_rr_lookup, rr_graph_view, grids, layer,
-                              clk_ntwk, verbose);
+  add_rr_graph_opin2clk_intermediate_edges(
+    rr_graph_builder, num_edges_to_create, clk_rr_lookup, rr_graph_view, grids,
+    layer, clk_ntwk, verbose);
 }
 
 /********************************************************************
diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp
index 2ff70bfc5..fd4ae69b9 100644
--- a/openfpga/src/annotation/route_clock_rr_graph.cpp
+++ b/openfpga/src/annotation/route_clock_rr_graph.cpp
@@ -455,8 +455,7 @@ static int rec_expand_and_route_clock_spine(
      * global net is mapped to the internal driver, use it as the previous
      * node  */
     size_t use_int_driver = 0;
-    if (!clk_ntwk.spine_intermediate_drivers(curr_spine, des_coord)
-           .empty() &&
+    if (!clk_ntwk.spine_intermediate_drivers(curr_spine, des_coord).empty() &&
         tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) {
       for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) {
         RRNodeId opin_node = rr_graph.edge_src_node(cand_edge);