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[FPGA-Verilog] Fixed a critical bug in verilog testbench generator for QL memory bank using BL/WL register which causes misalignment in shift register loading

This commit is contained in:
tangxifan 2021-10-03 16:04:47 -07:00
parent 28904ff526
commit 2badcb58f2
1 changed files with 2 additions and 2 deletions
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4
openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
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@ -647,7 +647,7 @@ void print_verilog_full_testbench_ql_memory_bank_shift_register_bitstream(std::f
fp << "if (";
fp << TOP_TB_BL_SHIFT_REGISTER_COUNT_PORT_NAME;
fp << " >= ";
fp << "`" << TOP_TB_BITSTREAM_BL_WORD_SIZE_VARIABLE;
fp << "`" << TOP_TB_BITSTREAM_BL_WORD_SIZE_VARIABLE << " - 1";
fp << ") begin";
fp << std::endl;
@ -691,7 +691,7 @@ void print_verilog_full_testbench_ql_memory_bank_shift_register_bitstream(std::f
fp << "if (";
fp << TOP_TB_WL_SHIFT_REGISTER_COUNT_PORT_NAME;
fp << " >= ";
fp << "`" << TOP_TB_BITSTREAM_WL_WORD_SIZE_VARIABLE;
fp << "`" << TOP_TB_BITSTREAM_WL_WORD_SIZE_VARIABLE << " - 1";
fp << ") begin";
fp << std::endl;