From 2b959290e90721d3bfb028324aea0df5839a3dd2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 13 Jan 2021 15:44:19 -0700 Subject: [PATCH] [Test] Deploy multi-clock test to CI --- .github/workflows/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/basic_reg_test.sh b/.github/workflows/basic_reg_test.sh index 1dbf7705c..875bbfd43 100755 --- a/.github/workflows/basic_reg_test.sh +++ b/.github/workflows/basic_reg_test.sh @@ -109,6 +109,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/til echo -e "Testing global port definition from tiles"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_logs echo -e "Testing yosys flow using custom ys script for running quicklogic device"; python3 openfpga_flow/scripts/run_fpga_task.py quicklogic_tests/flow_test --debug --show_thread_logs