diff --git a/openfpga_flow/tasks/mcnc_big20/config/task.conf b/openfpga_flow/tasks/mcnc_big20/config/task.conf
index 58ed4c714..da190286e 100644
--- a/openfpga_flow/tasks/mcnc_big20/config/task.conf
+++ b/openfpga_flow/tasks/mcnc_big20/config/task.conf
@@ -160,5 +160,6 @@ vpr_fpga_verilog_explicit_mapping=
 vpr_fpga_x2p_compact_routing_hierarchy=
 # If you wish to run Modelsim verification in batch, turn on the ini file outputting
 vpr_fpga_verilog_print_simulation_ini=
+# If you wish to run Modelsim verification in batch, turn off running iVerilog at the end of the flow
 #end_flow_with_test=
 
diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp
index bf70df367..e6f49a1c0 100644
--- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp
+++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp
@@ -208,8 +208,8 @@ size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary&
                num_ports_to_check,
                CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)],
                CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))], 
-               CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)],
-               ports.size());
+               ports.size(),
+               CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)]);
     num_err++;
   } 
   for (const auto& port : ports) {