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Updated documentation.

This commit is contained in:
Aram Kostanyan 2022-01-17 14:58:20 +05:00
parent 82067adc8c
commit 2b008177e7
2 changed files with 7 additions and 5 deletions
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docs/source/manual/openfpga_flow/run_fpga_flow.rst
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@ -109,7 +109,7 @@ General Arguments
.. option:: --yosys_tmpl <yosys_template_file>
This option allows the user to provide a custom Yosys template while running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Alternately, user can create a copy and modify according to their need. Yosys template script supports ``TOP_MODULE`` ``READ_VERILOG_FILE`` ``LUT_SIZE`` & ``OUTPUT_BLIF`` variables. In case if ``--verific`` option is provided then ``ADD_INCLUDE_DIR``, ``ADD_LIBRARY_DIR``, ``ADD_BLACKBOX_MODULES``, ``READ_HDL_FILE`` (should be used instead of ``READ_VERILOG_FILE``) and ``READ_LIBRARY`` additional varialbes are supported. The variables can be used as ``${var_name}``.
This option allows the user to provide a custom Yosys template while running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Alternately, user can create a copy and modify according to their need. Yosys template script supports ``TOP_MODULE`` ``READ_VERILOG_OPTIONS`` ``VERILOG_FILES`` ``LUT_SIZE`` & ``OUTPUT_BLIF`` variables. In case if ``--verific`` option is provided then ``ADD_INCLUDE_DIR``, ``ADD_LIBRARY_DIR``, ``ADD_BLACKBOX_MODULES``, ``READ_HDL_FILE`` (should be used instead of ``READ_VERILOG_OPTIONS`` and ``VERILOG_FILES``) and ``READ_LIBRARY`` additional varialbes are supported. The variables can be used as ``${var_name}``.
.. option:: --ys_rewrite_tmpl <yosys_rewrite_template_file>

10
docs/source/manual/openfpga_flow/run_fpga_task.rst
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@ -157,13 +157,15 @@ OpenFPGA_SHELL Sections
The option specifies VHDL language standard to be used while reading the VHDL files.
.. option:: verific_read_lib_name=<lib_name>
.. option:: verific_read_lib_name<lib_label>=<lib_name>
The option specifies library name where Verilog/SystemVerilog/VHDL files specified by ``verific_read_lib_src`` option will be loaded. This option should be used only with ``verific_read_lib_src`` option.
The ``lib_label`` variable can be any number of string without
white-spaces. The option specifies library name where Verilog/SystemVerilog/VHDL files specified by ``verific_read_lib_src<lib_label>`` option will be loaded. This option should be used only with ``verific_read_lib_src<lib_label>`` option.
.. option:: verific_read_lib_src=<library_src_files>
.. option:: verific_read_lib_src<lib_label>=<library_src_files>
The option specifies Verilog/SystemVerilog/VHDL files to be loaded into library specified by ``verific_read_lib_name`` option. The ``library_src_files`` should be the source files names separated by commas. This option should be used only with ``verific_read_lib_name`` option.
The ``lib_label`` variable can be any number of string without
white-spaces. The option specifies Verilog/SystemVerilog/VHDL files to be loaded into library specified by ``verific_read_lib_name<lib_label>`` option. The ``library_src_files`` should be the source files names separated by commas. This option should be used only with ``verific_read_lib_name<lib_label>`` option.
.. option:: verific_search_lib=<lib_name>