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[Architecture] Update architecture files for new latch naming

This commit is contained in:
tangxifan 2020-09-24 12:14:03 -06:00
parent fde15c4f88
commit 2add0406a7
11 changed files with 92 additions and 93 deletions
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15
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
View File

@ -146,28 +146,27 @@
<port type="sram" prefix="sram" size="16"/> <port type="sram" prefix="sram" size="16"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v"> <circuit_model type="sram" name="LATCH" prefix="LATCH" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="bl" prefix="bl" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="wl" prefix="wl" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
<port type="output" prefix="Qb" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v"> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/> <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/> <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="LATCH" default_val="1"/>
<port type="input" prefix="outpad" size="1"/> <port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/> <port type="output" prefix="inpad" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="frame_based" circuit_model_name="config_latch"/> <organization type="frame_based" circuit_model_name="LATCH"/>
</configuration_protocol> </configuration_protocol>
<connection_block> <connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>

18
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml
View File

@ -146,29 +146,29 @@
<port type="sram" prefix="sram" size="16"/> <port type="sram" prefix="sram" size="16"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_latch_set_reset" prefix="config_latch_set_reset" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch_set_reset.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch_set_reset.v"> <circuit_model type="sram" name="LATCHSR" prefix="LATCHSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="pSet" lib_name="set" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
<port type="bl" prefix="bl" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v"> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/> <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch_set_reset" default_val="1"/> <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="LATCHSR" default_val="1"/>
<port type="input" prefix="outpad" size="1"/> <port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/> <port type="output" prefix="inpad" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="frame_based" circuit_model_name="config_latch_set_reset"/> <organization type="frame_based" circuit_model_name="LATCHSR"/>
</configuration_protocol> </configuration_protocol>
<connection_block> <connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>

16
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml
View File

@ -146,28 +146,28 @@
<port type="sram" prefix="sram" size="16"/> <port type="sram" prefix="sram" size="16"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch_neg_rst.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch_neg_rst.v"> <circuit_model type="sram" name="LATCHRN" prefix="LATCHRN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="resetb" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RSTN" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v"> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/> <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/> <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="LATCHRN" default_val="1"/>
<port type="input" prefix="outpad" size="1"/> <port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/> <port type="output" prefix="inpad" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="frame_based" circuit_model_name="config_latch"/> <organization type="frame_based" circuit_model_name="LATCHRN"/>
</configuration_protocol> </configuration_protocol>
<connection_block> <connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>

16
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml
View File

@ -146,28 +146,28 @@
<port type="sram" prefix="sram" size="16"/> <port type="sram" prefix="sram" size="16"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_latch_set" prefix="config_latch_set" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch_set.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch_set.v"> <circuit_model type="sram" name="LATCHS" prefix="LATCHS" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pSet" lib_name="set" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
<port type="bl" prefix="bl" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v"> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/> <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch_set" default_val="1"/> <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="LATCHS" default_val="1"/>
<port type="input" prefix="outpad" size="1"/> <port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/> <port type="output" prefix="inpad" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="frame_based" circuit_model_name="config_latch_set"/> <organization type="frame_based" circuit_model_name="LATCHS"/>
</configuration_protocol> </configuration_protocol>
<connection_block> <connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>

16
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml
View File

@ -146,28 +146,28 @@
<port type="sram" prefix="sram" size="16"/> <port type="sram" prefix="sram" size="16"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_latch_neg_set" prefix="config_latch_neg_set" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch_neg_set.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch_neg_set.v"> <circuit_model type="sram" name="LATCHSN" prefix="LATCHSN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pSet" lib_name="setb" size="1" is_global="true" default_val="1" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SETN" size="1" is_global="true" default_val="1" is_set="true" is_prog="true"/>
<port type="bl" prefix="bl" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v"> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/> <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch_neg_set" default_val="1"/> <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="LATCHSN" default_val="1"/>
<port type="input" prefix="outpad" size="1"/> <port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/> <port type="output" prefix="inpad" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="frame_based" circuit_model_name="config_latch_neg_set"/> <organization type="frame_based" circuit_model_name="LATCHSN"/>
</configuration_protocol> </configuration_protocol>
<connection_block> <connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>

16
openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml
View File

@ -152,28 +152,28 @@
<port type="sram" prefix="sram" size="16"/> <port type="sram" prefix="sram" size="16"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v"> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/> <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/> <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
<port type="input" prefix="outpad" size="1"/> <port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/> <port type="output" prefix="inpad" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="frame_based" circuit_model_name="config_latch"/> <organization type="frame_based" circuit_model_name="LATCHR"/>
</configuration_protocol> </configuration_protocol>
<connection_block> <connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>

16
openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml
View File

@ -146,28 +146,28 @@
<port type="sram" prefix="sram" size="16"/> <port type="sram" prefix="sram" size="16"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v"> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/> <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/> <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
<port type="input" prefix="outpad" size="1"/> <port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/> <port type="output" prefix="inpad" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="frame_based" circuit_model_name="config_latch"/> <organization type="frame_based" circuit_model_name="LATCHR"/>
</configuration_protocol> </configuration_protocol>
<connection_block> <connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>

16
openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml
View File

@ -146,28 +146,28 @@
<port type="sram" prefix="sram" size="16"/> <port type="sram" prefix="sram" size="16"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v"> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/> <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/> <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
<port type="input" prefix="outpad" size="1"/> <port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/> <port type="output" prefix="inpad" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="frame_based" circuit_model_name="config_latch"/> <organization type="frame_based" circuit_model_name="LATCHR"/>
</configuration_protocol> </configuration_protocol>
<connection_block> <connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>

18
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
View File

@ -161,25 +161,25 @@
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/> <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/> <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="16"/> <port type="sram" prefix="sram" size="16"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/> <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v"> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/> <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/> <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
<port type="input" prefix="outpad" size="1"/> <port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/> <port type="output" prefix="inpad" size="1"/>
</circuit_model> </circuit_model>
@ -207,7 +207,7 @@
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="frame_based" circuit_model_name="config_latch"/> <organization type="frame_based" circuit_model_name="LATCHR"/>
</configuration_protocol> </configuration_protocol>
<connection_block> <connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>

18
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml
View File

@ -161,25 +161,25 @@
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/> <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/> <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="16"/> <port type="sram" prefix="sram" size="16"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/> <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v"> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/> <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/> <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
<port type="input" prefix="outpad" size="1"/> <port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/> <port type="output" prefix="inpad" size="1"/>
</circuit_model> </circuit_model>
@ -207,7 +207,7 @@
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="frame_based" circuit_model_name="config_latch"/> <organization type="frame_based" circuit_model_name="LATCHR"/>
</configuration_protocol> </configuration_protocol>
<connection_block> <connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>

20
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
View File

@ -161,25 +161,25 @@
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/> <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/> <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="16"/> <port type="sram" prefix="sram" size="16"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/> <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v"> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/> <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/> <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
<port type="input" prefix="outpad" size="1"/> <port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/> <port type="output" prefix="inpad" size="1"/>
</circuit_model> </circuit_model>
@ -213,11 +213,11 @@
<port type="input" prefix="b" size="32"/> <port type="input" prefix="b" size="32"/>
<port type="output" prefix="out" size="64"/> <port type="output" prefix="out" size="64"/>
<!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes --> <!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes -->
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="config_latch" default_val="1"/> <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="frame_based" circuit_model_name="config_latch"/> <organization type="frame_based" circuit_model_name="LATCHR"/>
</configuration_protocol> </configuration_protocol>
<connection_block> <connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>