Merge pull request #1896 from lnis-uofu/xt_vtr

[lib] update vtr to latest

libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp

@@ -6,7 +6,7 @@
 # Input file: /home/xifan/github/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd
 # md5sum of input file: 1db9d740309076fa51f61413bae1e072
 
-@0xb1073886de13324f;
+@0xdda3f3f93e497b0c;
 using Cxx = import "/capnp/c++.capnp";
 $Cxx.namespace("ucap");
 

openfpga/src/annotation/annotate_rr_graph.cpp

@@ -686,8 +686,9 @@ static void annotate_direct_circuit_models(
   VprDeviceAnnotation& vpr_device_annotation, const bool& verbose_output) {
   size_t count = 0;
 
-  for (int idirect = 0; idirect < vpr_device_ctx.arch->num_directs; ++idirect) {
+  for (size_t idirect = 0; idirect < vpr_device_ctx.arch->directs.size();
-    std::string direct_name = vpr_device_ctx.arch->Directs[idirect].name;
+       ++idirect) {
+    std::string direct_name = vpr_device_ctx.arch->directs[idirect].name;
     /* The name-to-circuit mapping is stored in either cb_switch-to-circuit or
      * sb_switch-to-circuit, Try to find one and update the device annotation
      */

openfpga/src/annotation/openfpga_annotate_routing.cpp

@@ -83,7 +83,8 @@ vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(
         VTR_LOG_ERROR(
           "When annotating global net '%s', invalid rr node pin type for '%s' "
           "pin '%d'\n",
-          cluster_nlist.net_name(net_id).c_str(), phy_tile->name, node_pin_num);
+          cluster_nlist.net_name(net_id).c_str(), phy_tile->name.c_str(),
+          node_pin_num);
         exit(1);
       }
       std::vector<RRNodeId> curr_rr_nodes =
@@ -91,7 +92,7 @@ vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(
           layer, blk_loc.loc.x, blk_loc.loc.y, rr_pin_type, node_pin_num);
       for (RRNodeId curr_rr_node : curr_rr_nodes) {
         VTR_LOGV(verbose, "Annotate global net '%s' on '%s' pin '%d'\n",
-                 cluster_nlist.net_name(net_id).c_str(), phy_tile->name,
+                 cluster_nlist.net_name(net_id).c_str(), phy_tile->name.c_str(),
                  node_pin_num);
         rr_node_nets[curr_rr_node] = net_id;
         counter++;

openfpga/src/base/openfpga_pb_pin_fixup.cpp

@@ -185,7 +185,7 @@ static int update_cluster_pin_with_post_routing_results(
         VTR_LOG_ERROR(
           "For tile '%s', found pin '%s' on %lu sides. Expect only 1. "
           "Following info is for debugging:\n",
-          physical_tile->name,
+          physical_tile->name.c_str(),
           get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)
             ->to_string()
             .c_str(),
@@ -204,7 +204,7 @@ static int update_cluster_pin_with_post_routing_results(
         VTR_LOG_ERROR(
           "For tile '%s', found pin '%s' on the boundary side '%s', which is "
           "not physically possible.\n",
-          physical_tile->name,
+          physical_tile->name.c_str(),
           get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)
             ->to_string()
             .c_str(),
@@ -215,7 +215,7 @@ static int update_cluster_pin_with_post_routing_results(
         VTR_LOG_ERROR(
           "For tile '%s', found pin '%s' on %lu sides. Expect only 1. "
           "Following info is for debugging:\n",
-          physical_tile->name,
+          physical_tile->name.c_str(),
           get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)
             ->to_string()
             .c_str(),
@@ -233,7 +233,7 @@ static int update_cluster_pin_with_post_routing_results(
         VTR_LOG_ERROR(
           "For boundary tile '%s', expect pin '%s' only on the side '%s' but "
           "found on the following sides:\n",
-          physical_tile->name,
+          physical_tile->name.c_str(),
           get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)
             ->to_string()
             .c_str(),

openfpga/src/fabric/build_fabric_io_location_map.cpp

@@ -76,7 +76,7 @@ static IoLocationMap build_fabric_fine_grained_io_location_map(
     if (size_t(phy_tile_type->capacity) !=
         module_manager.io_children(child).size()) {
       VTR_LOG("%s[%ld][%ld] capacity: %d while io_child number is %d",
-              phy_tile_type->name, coord.x(), coord.y(),
+              phy_tile_type->name.c_str(), coord.x(), coord.y(),
               phy_tile_type->capacity,
               module_manager.io_children(child).size());
     }
@@ -211,7 +211,7 @@ static IoLocationMap build_fabric_tiled_io_location_map(
       if (size_t(phy_tile_type->capacity) !=
           module_manager.io_children(tile_child).size()) {
         VTR_LOG("%s[%ld][%ld] capacity: %d while io_child number is %d",
-                phy_tile_type->name, coord.x(), coord.y(),
+                phy_tile_type->name.c_str(), coord.x(), coord.y(),
                 phy_tile_type->capacity,
                 module_manager.io_children(tile_child).size());
       }

openfpga/src/fpga_spice/spice_grid.cpp

@@ -290,10 +290,11 @@ static void print_spice_physical_tile_netlist(
   if (true == is_io_type(phy_block_type)) {
     SideManager side_manager(border_side);
     VTR_LOG("Writing SPICE Netlist '%s' for physical tile '%s' at %s side ...",
-            spice_fname.c_str(), phy_block_type->name, side_manager.c_str());
+            spice_fname.c_str(), phy_block_type->name.c_str(),
+            side_manager.c_str());
   } else {
     VTR_LOG("Writing SPICE Netlist '%s' for physical_tile '%s'...",
-            spice_fname.c_str(), phy_block_type->name);
+            spice_fname.c_str(), phy_block_type->name.c_str());
   }
 
   /* Create the file stream */

openfpga/src/fpga_verilog/verilog_grid.cpp

@@ -315,10 +315,11 @@ static void print_verilog_physical_tile_netlist(
     SideManager side_manager(border_side);
     VTR_LOG(
       "Writing Verilog Netlist '%s' for physical tile '%s' at %s side ...",
-      verilog_fpath.c_str(), phy_block_type->name, side_manager.c_str());
+      verilog_fpath.c_str(), phy_block_type->name.c_str(),
+      side_manager.c_str());
   } else {
     VTR_LOG("Writing Verilog Netlist '%s' for physical_tile '%s'...",
-            verilog_fpath.c_str(), phy_block_type->name);
+            verilog_fpath.c_str(), phy_block_type->name.c_str());
   }
 
   /* Create the file stream */

openfpga/src/repack/lb_router.cpp

@@ -441,7 +441,7 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
       VTR_LOG(
         "Net %lu '%s' is impossible to route within proposed %s cluster\n",
         inet, atom_nlist.net_name(lb_net_atom_net_ids_[NetId(inet)]).c_str(),
-        lb_type_->name);
+        lb_type_->name.c_str());
       VTR_LOG("\tNet source pin:\n");
       for (size_t isrc = 0; isrc < lb_net_sources_[NetId(inet)].size();
            ++isrc) {

openfpga/src/tile_direct/build_tile_direct.cpp

@@ -355,8 +355,9 @@ static void report_direct_from_port_and_to_port_mismatch(
     "From_port '%s[%lu:%lu] of direct '%s' does not match to_port "
     "'%s[%lu:%lu]'!\n",
     from_tile_port.get_name().c_str(), from_tile_port.get_lsb(),
-    from_tile_port.get_msb(), vpr_direct.name, to_tile_port.get_name().c_str(),
+    from_tile_port.get_msb(), vpr_direct.name.c_str(),
-    to_tile_port.get_lsb(), to_tile_port.get_msb());
+    to_tile_port.get_name().c_str(), to_tile_port.get_lsb(),
+    to_tile_port.get_msb());
 }
 
 /***************************************************************************************
@@ -794,28 +795,29 @@ TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
   TileDirect tile_direct;
 
   /* Walk through each direct definition in the VPR arch */
-  for (int idirect = 0; idirect < device_ctx.arch->num_directs; ++idirect) {
+  for (size_t idirect = 0; idirect < device_ctx.arch->directs.size();
+       ++idirect) {
     ArchDirectId arch_direct_id =
-      arch_direct.direct(std::string(device_ctx.arch->Directs[idirect].name));
+      arch_direct.direct(std::string(device_ctx.arch->directs[idirect].name));
     if (ArchDirectId::INVALID() == arch_direct_id) {
       VTR_LOG_ERROR(
         "Unable to find an annotation in openfpga architecture XML for "
         "<direct> '%s'!\n",
-        device_ctx.arch->Directs[idirect].name);
+        device_ctx.arch->directs[idirect].name.c_str());
       exit(1);
     }
     /* Build from original VPR arch definition */
     if (e_direct_type::INNER_COLUMN_OR_ROW ==
         arch_direct.type(arch_direct_id)) {
       build_inner_column_row_tile_direct(tile_direct,
-                                         device_ctx.arch->Directs[idirect],
+                                         device_ctx.arch->directs[idirect],
                                          device_ctx, arch_direct_id, verbose);
       /* Skip those direct connections which belong part of a connection block
        */
     }
     /* Build from OpenFPGA arch definition */
     build_inter_column_row_tile_direct(
-      tile_direct, device_ctx.arch->Directs[idirect], device_ctx, arch_direct,
+      tile_direct, device_ctx.arch->directs[idirect], device_ctx, arch_direct,
       arch_direct_id, verbose);
   }
 

openfpga/src/utils/check_tile_annotation.cpp

@@ -181,7 +181,7 @@ static int check_tile_annotation_conflicts_with_physical_tile(
                 required_tile_port.get_name().c_str(),
                 required_tile_port.get_lsb(), required_tile_port.get_msb(),
                 tile_annotation.global_port_name(tile_global_port).c_str(),
-                physical_tile.name, tile_port.name);
+                physical_tile.name.c_str(), tile_port.name);
               num_err++;
             }
 
@@ -196,7 +196,7 @@ static int check_tile_annotation_conflicts_with_physical_tile(
                 required_tile_port.get_name().c_str(),
                 required_tile_port.get_lsb(), required_tile_port.get_msb(),
                 tile_annotation.global_port_name(tile_global_port).c_str(),
-                physical_tile.name, tile_port.name);
+                physical_tile.name.c_str(), tile_port.name);
               num_err++;
             }
 
@@ -211,7 +211,7 @@ static int check_tile_annotation_conflicts_with_physical_tile(
                 required_tile_port.get_name().c_str(),
                 required_tile_port.get_lsb(), required_tile_port.get_msb(),
                 tile_annotation.global_port_name(tile_global_port).c_str(),
-                physical_tile.name, tile_port.name, pin_Fc);
+                physical_tile.name.c_str(), tile_port.name, pin_Fc);
             }
 
             found_matched_physical_tile_port++;

openfpga/src/utils/openfpga_physical_tile_utils.cpp

@@ -72,7 +72,7 @@ float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type, const int& pin) {
   }
   /* Every pin should have a Fc, give a wrong value */
   VTR_LOGF_ERROR(__FILE__, __LINE__, "Fail to find the Fc for %s.pin[%lu]\n",
-                 type->name, pin);
+                 type->name.c_str(), pin);
   exit(1);
 }
 

openfpga_flow/scripts/run_fpga_flow.py

@@ -1017,17 +1017,17 @@ def run_command(taskname, logfile, command, exit_if_fail=True):
         try:
             output.write(" ".join(command) + "\n")
             process = subprocess.run(
-                command, stdout=subprocess.PIPE, stderr=subprocess.PIPE, universal_newlines=True
+                command, stdout=subprocess.PIPE, stderr=subprocess.PIPE, universal_newlines=False
             )
-            output.write(process.stdout)
+            output.write(process.stdout.decode("cp1252"))
-            output.write(process.stderr)
+            output.write(process.stderr.decode("cp1252"))
             output.write(str(process.returncode))
             if "openfpgashell" in logfile:
-                filter_openfpga_output(process.stdout)
+                filter_openfpga_output(process.stdout.decode("cp1252"))
             if process.returncode:
                 logger.error("%s run failed with returncode %d" % (taskname, process.returncode))
                 logger.error("command %s" % " ".join(command))
-                filter_failed_process_output(process.stderr)
+                filter_failed_process_output(process.stderr.decode("cp1252"))
                 if exit_if_fail:
                     clean_up_and_exit("Failed to run %s task" % taskname)
         except Exception:
@@ -1036,7 +1036,7 @@ def run_command(taskname, logfile, command, exit_if_fail=True):
             if exit_if_fail:
                 clean_up_and_exit("Failed to run %s task" % taskname)
     logger.info("%s is written in file %s" % (taskname, logfile))
-    return process.stdout
+    return process.stdout.decode("cp1252")
 
 
 def filter_openfpga_output(vpr_output):

openfpga_flow/scripts/run_fpga_task.py

@@ -542,7 +542,7 @@ def strip_child_logger_info(line):
 
 def run_single_script(s, eachJob, job_list):
     with s:
-        thread_name = threading.currentThread().getName()
+        thread_name = threading.current_thread().name
         eachJob["starttime"] = time.time()
         try:
             logfile = "%s_out.log" % thread_name

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf

@@ -53,6 +53,8 @@ bench1_openfpga_vpr_route_chan_width=44
 
 bench2_top = rst_and_clk_on_lut
 bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml
+# Triggered a bug in VPR, when route_chan_width=40, it failed
+bench2_openfpga_vpr_route_chan_width=44
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=

openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v

@@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb;
 	initial begin
 		clk[0] <= 1'b0;
 		while(1) begin
-			#0.809066534
+			#0.4880859554
 			clk[0] <= !clk[0];
 		end
 	end
@@ -106,7 +106,7 @@ initial begin
 	$timeformat(-9, 2, "ns", 20);
 	$display("Simulation start");
 // ----- Can be changed by the user for his/her need -------
-	#11.32693195
+	#6.833203316
 	if(nb_error == 0) begin
 		$display("Simulation Succeed");
 	end else begin

openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc

@@ -9,20 +9,19 @@
 ##################################################
 # Create clock                                    
 ##################################################
-create_clock clk[0] -period 1.618133072e-09 -waveform {0 8.09066536e-10}
+create_clock clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10}
 
 ##################################################
 # Create input and output delays for used I/Os    
 ##################################################
-set_input_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[11]
+set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[11]
-set_input_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[14]
+set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[14]
-set_output_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[12]
+set_output_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[1]
 
 ##################################################
 # Disable timing for unused I/Os    
 ##################################################
 set_disable_timing gfpga_pad_GPIO_PAD[0]
-set_disable_timing gfpga_pad_GPIO_PAD[1]
 set_disable_timing gfpga_pad_GPIO_PAD[2]
 set_disable_timing gfpga_pad_GPIO_PAD[3]
 set_disable_timing gfpga_pad_GPIO_PAD[4]
@@ -32,6 +31,7 @@ set_disable_timing gfpga_pad_GPIO_PAD[7]
 set_disable_timing gfpga_pad_GPIO_PAD[8]
 set_disable_timing gfpga_pad_GPIO_PAD[9]
 set_disable_timing gfpga_pad_GPIO_PAD[10]
+set_disable_timing gfpga_pad_GPIO_PAD[12]
 set_disable_timing gfpga_pad_GPIO_PAD[13]
 set_disable_timing gfpga_pad_GPIO_PAD[15]
 set_disable_timing gfpga_pad_GPIO_PAD[16]
@@ -156,9 +156,11 @@ set_disable_timing cbx_1__0_/chanx_left_in[7]
 set_disable_timing cbx_1__0_/chanx_right_in[7]
 set_disable_timing cbx_1__0_/chanx_left_in[8]
 set_disable_timing cbx_1__0_/chanx_right_in[8]
+set_disable_timing cbx_1__0_/chanx_left_in[9]
 set_disable_timing cbx_1__0_/chanx_right_in[9]
 set_disable_timing cbx_1__0_/chanx_left_in[10]
 set_disable_timing cbx_1__0_/chanx_right_in[10]
+set_disable_timing cbx_1__0_/chanx_left_in[11]
 set_disable_timing cbx_1__0_/chanx_right_in[11]
 set_disable_timing cbx_1__0_/chanx_left_in[12]
 set_disable_timing cbx_1__0_/chanx_right_in[12]
@@ -180,9 +182,11 @@ set_disable_timing cbx_1__0_/chanx_left_out[7]
 set_disable_timing cbx_1__0_/chanx_right_out[7]
 set_disable_timing cbx_1__0_/chanx_left_out[8]
 set_disable_timing cbx_1__0_/chanx_right_out[8]
+set_disable_timing cbx_1__0_/chanx_left_out[9]
 set_disable_timing cbx_1__0_/chanx_right_out[9]
 set_disable_timing cbx_1__0_/chanx_left_out[10]
 set_disable_timing cbx_1__0_/chanx_right_out[10]
+set_disable_timing cbx_1__0_/chanx_left_out[11]
 set_disable_timing cbx_1__0_/chanx_right_out[11]
 set_disable_timing cbx_1__0_/chanx_left_out[12]
 set_disable_timing cbx_1__0_/chanx_right_out[12]
@@ -272,6 +276,7 @@ set_disable_timing cbx_1__1_/chanx_left_in[1]
 set_disable_timing cbx_1__1_/chanx_left_in[2]
 set_disable_timing cbx_1__1_/chanx_right_in[2]
 set_disable_timing cbx_1__1_/chanx_left_in[3]
+set_disable_timing cbx_1__1_/chanx_right_in[3]
 set_disable_timing cbx_1__1_/chanx_left_in[4]
 set_disable_timing cbx_1__1_/chanx_right_in[4]
 set_disable_timing cbx_1__1_/chanx_left_in[5]
@@ -296,6 +301,7 @@ set_disable_timing cbx_1__1_/chanx_left_out[1]
 set_disable_timing cbx_1__1_/chanx_left_out[2]
 set_disable_timing cbx_1__1_/chanx_right_out[2]
 set_disable_timing cbx_1__1_/chanx_left_out[3]
+set_disable_timing cbx_1__1_/chanx_right_out[3]
 set_disable_timing cbx_1__1_/chanx_left_out[4]
 set_disable_timing cbx_1__1_/chanx_right_out[4]
 set_disable_timing cbx_1__1_/chanx_left_out[5]
@@ -315,7 +321,6 @@ set_disable_timing cbx_1__1_/chanx_right_out[11]
 set_disable_timing cbx_1__1_/chanx_left_out[12]
 set_disable_timing cbx_1__1_/chanx_right_out[12]
 set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0]
-set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0]
 set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0]
 set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0]
 set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0]
@@ -334,7 +339,6 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[0]
 set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[3]
 set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[1]
 set_disable_timing cbx_1__1_/mux_top_ipin_0/in[1]
-set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[2]
 set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[0]
 set_disable_timing cbx_1__1_/mux_top_ipin_0/in[0]
 set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[3]
@@ -411,9 +415,11 @@ set_disable_timing cby_0__1_/chany_top_in[6]
 set_disable_timing cby_0__1_/chany_bottom_in[7]
 set_disable_timing cby_0__1_/chany_top_in[7]
 set_disable_timing cby_0__1_/chany_bottom_in[8]
+set_disable_timing cby_0__1_/chany_top_in[8]
 set_disable_timing cby_0__1_/chany_bottom_in[9]
 set_disable_timing cby_0__1_/chany_top_in[9]
 set_disable_timing cby_0__1_/chany_bottom_in[10]
+set_disable_timing cby_0__1_/chany_top_in[10]
 set_disable_timing cby_0__1_/chany_bottom_in[11]
 set_disable_timing cby_0__1_/chany_top_in[11]
 set_disable_timing cby_0__1_/chany_bottom_in[12]
@@ -435,9 +441,11 @@ set_disable_timing cby_0__1_/chany_top_out[6]
 set_disable_timing cby_0__1_/chany_bottom_out[7]
 set_disable_timing cby_0__1_/chany_top_out[7]
 set_disable_timing cby_0__1_/chany_bottom_out[8]
+set_disable_timing cby_0__1_/chany_top_out[8]
 set_disable_timing cby_0__1_/chany_bottom_out[9]
 set_disable_timing cby_0__1_/chany_top_out[9]
 set_disable_timing cby_0__1_/chany_bottom_out[10]
+set_disable_timing cby_0__1_/chany_top_out[10]
 set_disable_timing cby_0__1_/chany_bottom_out[11]
 set_disable_timing cby_0__1_/chany_top_out[11]
 set_disable_timing cby_0__1_/chany_bottom_out[12]
@@ -518,9 +526,11 @@ set_disable_timing cby_0__1_/mux_right_ipin_4/in[4]
 set_disable_timing cby_1__1_/chany_top_in[0]
 set_disable_timing cby_1__1_/chany_bottom_in[1]
 set_disable_timing cby_1__1_/chany_top_in[1]
+set_disable_timing cby_1__1_/chany_bottom_in[2]
 set_disable_timing cby_1__1_/chany_top_in[2]
 set_disable_timing cby_1__1_/chany_bottom_in[3]
 set_disable_timing cby_1__1_/chany_top_in[3]
+set_disable_timing cby_1__1_/chany_bottom_in[4]
 set_disable_timing cby_1__1_/chany_top_in[4]
 set_disable_timing cby_1__1_/chany_bottom_in[5]
 set_disable_timing cby_1__1_/chany_top_in[5]
@@ -539,9 +549,11 @@ set_disable_timing cby_1__1_/chany_top_in[12]
 set_disable_timing cby_1__1_/chany_top_out[0]
 set_disable_timing cby_1__1_/chany_bottom_out[1]
 set_disable_timing cby_1__1_/chany_top_out[1]
+set_disable_timing cby_1__1_/chany_bottom_out[2]
 set_disable_timing cby_1__1_/chany_top_out[2]
 set_disable_timing cby_1__1_/chany_bottom_out[3]
 set_disable_timing cby_1__1_/chany_top_out[3]
+set_disable_timing cby_1__1_/chany_bottom_out[4]
 set_disable_timing cby_1__1_/chany_top_out[4]
 set_disable_timing cby_1__1_/chany_bottom_out[5]
 set_disable_timing cby_1__1_/chany_top_out[5]
@@ -561,6 +573,7 @@ set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_out
 set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0]
 set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0]
 set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0]
+set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0]
 set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0]
 set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0]
 set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0]
@@ -589,6 +602,7 @@ set_disable_timing cby_1__1_/mux_right_ipin_2/in[1]
 set_disable_timing cby_1__1_/mux_left_ipin_3/in[2]
 set_disable_timing cby_1__1_/mux_left_ipin_4/in[0]
 set_disable_timing cby_1__1_/mux_right_ipin_2/in[0]
+set_disable_timing cby_1__1_/mux_left_ipin_4/in[3]
 set_disable_timing cby_1__1_/mux_left_ipin_5/in[1]
 set_disable_timing cby_1__1_/mux_left_ipin_4/in[2]
 set_disable_timing cby_1__1_/mux_left_ipin_5/in[0]
@@ -648,9 +662,11 @@ set_disable_timing sb_0__0_/chany_top_in[6]
 set_disable_timing sb_0__0_/chany_top_out[7]
 set_disable_timing sb_0__0_/chany_top_in[7]
 set_disable_timing sb_0__0_/chany_top_out[8]
+set_disable_timing sb_0__0_/chany_top_in[8]
 set_disable_timing sb_0__0_/chany_top_out[9]
 set_disable_timing sb_0__0_/chany_top_in[9]
 set_disable_timing sb_0__0_/chany_top_out[10]
+set_disable_timing sb_0__0_/chany_top_in[10]
 set_disable_timing sb_0__0_/chany_top_out[11]
 set_disable_timing sb_0__0_/chany_top_in[11]
 set_disable_timing sb_0__0_/chany_top_out[12]
@@ -673,9 +689,11 @@ set_disable_timing sb_0__0_/chanx_right_out[7]
 set_disable_timing sb_0__0_/chanx_right_in[7]
 set_disable_timing sb_0__0_/chanx_right_out[8]
 set_disable_timing sb_0__0_/chanx_right_in[8]
+set_disable_timing sb_0__0_/chanx_right_out[9]
 set_disable_timing sb_0__0_/chanx_right_in[9]
 set_disable_timing sb_0__0_/chanx_right_out[10]
 set_disable_timing sb_0__0_/chanx_right_in[10]
+set_disable_timing sb_0__0_/chanx_right_out[11]
 set_disable_timing sb_0__0_/chanx_right_in[11]
 set_disable_timing sb_0__0_/chanx_right_out[12]
 set_disable_timing sb_0__0_/chanx_right_in[12]
@@ -757,7 +775,9 @@ set_disable_timing sb_0__0_/mux_right_track_10/in[0]
 set_disable_timing sb_0__0_/mux_right_track_12/in[0]
 set_disable_timing sb_0__0_/mux_right_track_14/in[0]
 set_disable_timing sb_0__0_/mux_right_track_16/in[0]
+set_disable_timing sb_0__0_/mux_right_track_18/in[0]
 set_disable_timing sb_0__0_/mux_right_track_20/in[0]
+set_disable_timing sb_0__0_/mux_right_track_22/in[0]
 set_disable_timing sb_0__0_/mux_right_track_24/in[0]
 set_disable_timing sb_0__0_/mux_right_track_0/in[0]
 set_disable_timing sb_0__0_/mux_top_track_24/in[2]
@@ -782,6 +802,7 @@ set_disable_timing sb_0__1_/chanx_right_out[1]
 set_disable_timing sb_0__1_/chanx_right_out[2]
 set_disable_timing sb_0__1_/chanx_right_in[2]
 set_disable_timing sb_0__1_/chanx_right_out[3]
+set_disable_timing sb_0__1_/chanx_right_in[3]
 set_disable_timing sb_0__1_/chanx_right_out[4]
 set_disable_timing sb_0__1_/chanx_right_in[4]
 set_disable_timing sb_0__1_/chanx_right_out[5]
@@ -817,9 +838,11 @@ set_disable_timing sb_0__1_/chany_bottom_out[6]
 set_disable_timing sb_0__1_/chany_bottom_in[7]
 set_disable_timing sb_0__1_/chany_bottom_out[7]
 set_disable_timing sb_0__1_/chany_bottom_in[8]
+set_disable_timing sb_0__1_/chany_bottom_out[8]
 set_disable_timing sb_0__1_/chany_bottom_in[9]
 set_disable_timing sb_0__1_/chany_bottom_out[9]
 set_disable_timing sb_0__1_/chany_bottom_in[10]
+set_disable_timing sb_0__1_/chany_bottom_out[10]
 set_disable_timing sb_0__1_/chany_bottom_in[11]
 set_disable_timing sb_0__1_/chany_bottom_out[11]
 set_disable_timing sb_0__1_/chany_bottom_in[12]
@@ -893,7 +916,9 @@ set_disable_timing sb_0__1_/mux_bottom_track_3/in[3]
 set_disable_timing sb_0__1_/mux_bottom_track_15/in[3]
 set_disable_timing sb_0__1_/mux_bottom_track_17/in[2]
 set_disable_timing sb_0__1_/mux_bottom_track_23/in[0]
+set_disable_timing sb_0__1_/mux_bottom_track_21/in[0]
 set_disable_timing sb_0__1_/mux_bottom_track_19/in[0]
+set_disable_timing sb_0__1_/mux_bottom_track_17/in[0]
 set_disable_timing sb_0__1_/mux_bottom_track_15/in[0]
 set_disable_timing sb_0__1_/mux_bottom_track_13/in[0]
 set_disable_timing sb_0__1_/mux_bottom_track_11/in[0]
@@ -922,9 +947,11 @@ set_disable_timing sb_0__1_/mux_right_track_24/in[2]
 set_disable_timing sb_1__0_/chany_top_in[0]
 set_disable_timing sb_1__0_/chany_top_out[1]
 set_disable_timing sb_1__0_/chany_top_in[1]
+set_disable_timing sb_1__0_/chany_top_out[2]
 set_disable_timing sb_1__0_/chany_top_in[2]
 set_disable_timing sb_1__0_/chany_top_out[3]
 set_disable_timing sb_1__0_/chany_top_in[3]
+set_disable_timing sb_1__0_/chany_top_out[4]
 set_disable_timing sb_1__0_/chany_top_in[4]
 set_disable_timing sb_1__0_/chany_top_out[5]
 set_disable_timing sb_1__0_/chany_top_in[5]
@@ -958,9 +985,11 @@ set_disable_timing sb_1__0_/chanx_left_in[7]
 set_disable_timing sb_1__0_/chanx_left_out[7]
 set_disable_timing sb_1__0_/chanx_left_in[8]
 set_disable_timing sb_1__0_/chanx_left_out[8]
+set_disable_timing sb_1__0_/chanx_left_in[9]
 set_disable_timing sb_1__0_/chanx_left_out[9]
 set_disable_timing sb_1__0_/chanx_left_in[10]
 set_disable_timing sb_1__0_/chanx_left_out[10]
+set_disable_timing sb_1__0_/chanx_left_in[11]
 set_disable_timing sb_1__0_/chanx_left_out[11]
 set_disable_timing sb_1__0_/chanx_left_in[12]
 set_disable_timing sb_1__0_/chanx_left_out[12]
@@ -1050,7 +1079,9 @@ set_disable_timing sb_1__0_/mux_top_track_16/in[2]
 set_disable_timing sb_1__0_/mux_top_track_14/in[3]
 set_disable_timing sb_1__0_/mux_top_track_12/in[2]
 set_disable_timing sb_1__0_/mux_top_track_10/in[2]
+set_disable_timing sb_1__0_/mux_top_track_8/in[2]
 set_disable_timing sb_1__0_/mux_top_track_6/in[2]
+set_disable_timing sb_1__0_/mux_top_track_4/in[2]
 set_disable_timing sb_1__0_/mux_top_track_2/in[3]
 ##################################################
 # Disable timing for Switch block sb_1__1_
@@ -1058,9 +1089,11 @@ set_disable_timing sb_1__0_/mux_top_track_2/in[3]
 set_disable_timing sb_1__1_/chany_bottom_out[0]
 set_disable_timing sb_1__1_/chany_bottom_in[1]
 set_disable_timing sb_1__1_/chany_bottom_out[1]
+set_disable_timing sb_1__1_/chany_bottom_in[2]
 set_disable_timing sb_1__1_/chany_bottom_out[2]
 set_disable_timing sb_1__1_/chany_bottom_in[3]
 set_disable_timing sb_1__1_/chany_bottom_out[3]
+set_disable_timing sb_1__1_/chany_bottom_in[4]
 set_disable_timing sb_1__1_/chany_bottom_out[4]
 set_disable_timing sb_1__1_/chany_bottom_in[5]
 set_disable_timing sb_1__1_/chany_bottom_out[5]
@@ -1082,6 +1115,7 @@ set_disable_timing sb_1__1_/chanx_left_in[1]
 set_disable_timing sb_1__1_/chanx_left_in[2]
 set_disable_timing sb_1__1_/chanx_left_out[2]
 set_disable_timing sb_1__1_/chanx_left_in[3]
+set_disable_timing sb_1__1_/chanx_left_out[3]
 set_disable_timing sb_1__1_/chanx_left_in[4]
 set_disable_timing sb_1__1_/chanx_left_out[4]
 set_disable_timing sb_1__1_/chanx_left_in[5]
@@ -1166,6 +1200,7 @@ set_disable_timing sb_1__1_/mux_left_track_13/in[3]
 set_disable_timing sb_1__1_/mux_left_track_15/in[2]
 set_disable_timing sb_1__1_/mux_left_track_17/in[2]
 set_disable_timing sb_1__1_/mux_left_track_5/in[0]
+set_disable_timing sb_1__1_/mux_left_track_7/in[0]
 set_disable_timing sb_1__1_/mux_left_track_9/in[0]
 set_disable_timing sb_1__1_/mux_left_track_11/in[0]
 set_disable_timing sb_1__1_/mux_left_track_13/in[0]
@@ -1431,16 +1466,20 @@ set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/*
 #######################################
 set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/*
 #######################################
-# Disable Timing for unused grid[1][2][1]
+# Disable Timing for unused resources in grid[1][2][1]
 #######################################
 #######################################
-# Disable all the ports for pb_graph_node io[0]
+# Disable unused pins for pb_graph_node io[0]
 #######################################
-set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/*
+set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/io_inpad[0]
 #######################################
-# Disable all the ports for pb_graph_node iopad[0]
+# Disable unused mux_inputs for pb_graph_node io[0]
 #######################################
-set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
+set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1//direct_interc_0_/in[0]
+#######################################
+# Disable unused pins for pb_graph_node iopad[0]
+#######################################
+set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
 #######################################
 # Disable Timing for unused grid[1][2][2]
 #######################################
@@ -1559,20 +1598,16 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3//direct_interc
 #######################################
 set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
 #######################################
-# Disable Timing for unused resources in grid[2][1][4]
+# Disable Timing for unused grid[2][1][4]
 #######################################
 #######################################
-# Disable unused pins for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node io[0]
 #######################################
-set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/io_inpad[0]
+set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/*
 #######################################
-# Disable unused mux_inputs for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node iopad[0]
 #######################################
-set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4//direct_interc_0_/in[0]
+set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/*
-#######################################
-# Disable unused pins for pb_graph_node iopad[0]
-#######################################
-set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
 #######################################
 # Disable Timing for unused grid[2][1][5]
 #######################################

openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v

@@ -45,12 +45,11 @@ wire [0:0] clk_fm;
 // ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[14] -----
 	assign gfpga_pad_GPIO_PAD_fm[14] = b[0];
 
-// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
+// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[1] -----
-	assign c[0] = gfpga_pad_GPIO_PAD_fm[12];
+	assign c[0] = gfpga_pad_GPIO_PAD_fm[1];
 
 // ----- Wire unused FPGA I/Os to constants -----
 	assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
-	assign gfpga_pad_GPIO_PAD_fm[1] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[2] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[3] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[4] = 1'b0;
@@ -60,6 +59,7 @@ wire [0:0] clk_fm;
 	assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
+	assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0;
@@ -132,8 +132,8 @@ initial begin
 	force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1000;
 	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
 	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
-	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
+	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
-	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
+	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
 	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
 	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
 	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
@@ -154,8 +154,8 @@ initial begin
 	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
 	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
 	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
-	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
+	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
-	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
+	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
 	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
 	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
 	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
@@ -238,12 +238,12 @@ initial begin
 	force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}};
@@ -288,12 +288,12 @@ initial begin
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}};
-	force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}};
@@ -302,12 +302,12 @@ initial begin
 	force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}};
-	force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10;
+	force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01;
+	force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = 2'b10;
+	force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = 2'b01;
+	force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}};
@@ -382,8 +382,8 @@ initial begin
 	force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
@@ -426,8 +426,8 @@ initial begin
 	force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
-	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
+	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = 3'b001;
-	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
+	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = 3'b110;
 	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}};
@@ -474,8 +474,8 @@ initial begin
 	force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}};
-	force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = 3'b101;
+	force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}};
-	force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = 3'b010;
+	force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}};

openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit

@@ -155,31 +155,6 @@
 0
 0
 0
-1
-0
-1
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
 0
 0
 0
@@ -223,7 +198,32 @@
 0
 0
 1
-1
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
 0
 0
 1
@@ -301,12 +301,12 @@
 0
 0
 0
-1
-1
 0
 0
-1
+0
-1
+0
+0
+0
 0
 0
 0
@@ -360,11 +360,6 @@
 1
 1
 1
-1
-1
-1
-1
-1
 0
 1
 1
@@ -378,6 +373,11 @@
 1
 1
 1
+1
+1
+1
+1
+1
 0
 0
 0
@@ -459,11 +459,11 @@
 0
 0
 0
-1
 0
 0
 0
-1
+0
+0
 0
 0
 0
@@ -472,12 +472,12 @@
 1
 0
 0
-1
+0
-1
+0
-0
+0
-0
+0
-1
+0
-1
+0
 0
 0
 0

openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml

@@ -314,11 +314,11 @@
 		</bit>
 		<bit id="373" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_5.mem_out[0]">
 		</bit>
-		<bit id="372" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[2]">
+		<bit id="372" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[2]">
 		</bit>
 		<bit id="371" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[1]">
 		</bit>
-		<bit id="370" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[0]">
+		<bit id="370" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[0]">
 		</bit>
 		<bit id="369" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[2]">
 		</bit>
@@ -398,7 +398,7 @@
 		</bit>
 		<bit id="331" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_2.mem_out[0]">
 		</bit>
-		<bit id="330" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_1.mem_out[2]">
+		<bit id="330" value="1" path="fpga_top.cbx_1__1_.mem_bottom_ipin_1.mem_out[2]">
 		</bit>
 		<bit id="329" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_1.mem_out[1]">
 		</bit>
@@ -448,9 +448,9 @@
 		</bit>
 		<bit id="306" value="0" path="fpga_top.sb_1__1_.mem_left_track_9.mem_out[0]">
 		</bit>
-		<bit id="305" value="1" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[1]">
+		<bit id="305" value="0" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[1]">
 		</bit>
-		<bit id="304" value="1" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[0]">
+		<bit id="304" value="0" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[0]">
 		</bit>
 		<bit id="303" value="0" path="fpga_top.sb_1__1_.mem_left_track_5.mem_out[1]">
 		</bit>
@@ -606,17 +606,17 @@
 		</bit>
 		<bit id="227" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_23.mem_out[0]">
 		</bit>
-		<bit id="226" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[1]">
+		<bit id="226" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[1]">
 		</bit>
-		<bit id="225" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[0]">
+		<bit id="225" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[0]">
 		</bit>
 		<bit id="224" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_19.mem_out[1]">
 		</bit>
 		<bit id="223" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_19.mem_out[0]">
 		</bit>
-		<bit id="222" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[1]">
+		<bit id="222" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[1]">
 		</bit>
-		<bit id="221" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[0]">
+		<bit id="221" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[0]">
 		</bit>
 		<bit id="220" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_15.mem_out[2]">
 		</bit>
@@ -724,7 +724,7 @@
 		</bit>
 		<bit id="168" value="1" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
 		</bit>
-		<bit id="167" value="1" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
+		<bit id="167" value="0" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
 		</bit>
 		<bit id="166" value="1" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
 		</bit>
@@ -734,7 +734,7 @@
 		</bit>
 		<bit id="163" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
 		</bit>
-		<bit id="162" value="0" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
+		<bit id="162" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
 		</bit>
 		<bit id="161" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
 		</bit>
@@ -922,7 +922,7 @@
 		</bit>
 		<bit id="69" value="0" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[1]">
 		</bit>
-		<bit id="68" value="1" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[0]">
+		<bit id="68" value="0" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[0]">
 		</bit>
 		<bit id="67" value="0" path="fpga_top.sb_1__0_.mem_top_track_6.mem_out[1]">
 		</bit>
@@ -930,7 +930,7 @@
 		</bit>
 		<bit id="65" value="0" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[1]">
 		</bit>
-		<bit id="64" value="1" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[0]">
+		<bit id="64" value="0" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[0]">
 		</bit>
 		<bit id="63" value="0" path="fpga_top.sb_1__0_.mem_top_track_2.mem_out[2]">
 		</bit>
@@ -948,17 +948,17 @@
 		</bit>
 		<bit id="56" value="0" path="fpga_top.sb_0__0_.mem_right_track_24.mem_out[0]">
 		</bit>
-		<bit id="55" value="1" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[1]">
+		<bit id="55" value="0" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[1]">
 		</bit>
-		<bit id="54" value="1" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[0]">
+		<bit id="54" value="0" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[0]">
 		</bit>
 		<bit id="53" value="0" path="fpga_top.sb_0__0_.mem_right_track_20.mem_out[1]">
 		</bit>
 		<bit id="52" value="0" path="fpga_top.sb_0__0_.mem_right_track_20.mem_out[0]">
 		</bit>
-		<bit id="51" value="1" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[1]">
+		<bit id="51" value="0" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[1]">
 		</bit>
-		<bit id="50" value="1" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[0]">
+		<bit id="50" value="0" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[0]">
 		</bit>
 		<bit id="49" value="0" path="fpga_top.sb_0__0_.mem_right_track_16.mem_out[1]">
 		</bit>

openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml

@@ -553,7 +553,7 @@
 						<instance level="4" name="GPIO_DFF_mem"/>
 					</hierarchy>
 					<bitstream>
-						<bit memory_port="mem_out[0]" value="1"/>
+						<bit memory_port="mem_out[0]" value="0"/>
 					</bitstream>
 				</bitstream_block>
 			</bitstream_block>
@@ -731,7 +731,7 @@
 						<instance level="4" name="GPIO_DFF_mem"/>
 					</hierarchy>
 					<bitstream>
-						<bit memory_port="mem_out[0]" value="0"/>
+						<bit memory_port="mem_out[0]" value="1"/>
 					</bitstream>
 				</bitstream_block>
 			</bitstream_block>
@@ -1480,15 +1480,15 @@
 				<instance level="2" name="mem_right_track_18"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_right_track_20" hierarchy_level="2">
@@ -1516,15 +1516,15 @@
 				<instance level="2" name="mem_right_track_22"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_right_track_24" hierarchy_level="2">
@@ -1961,16 +1961,16 @@
 				<instance level="2" name="mem_bottom_track_17"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_bottom_track_19" hierarchy_level="2">
@@ -2002,11 +2002,11 @@
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_bottom_track_23" hierarchy_level="2">
@@ -2098,13 +2098,13 @@
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="c"/>
+				<path id="2" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="2">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
 				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
@@ -2136,13 +2136,13 @@
 			<input_nets>
 				<path id="0" net_name="a"/>
 				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="c"/>
+				<path id="2" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="2">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
 				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
@@ -2864,16 +2864,16 @@
 				<instance level="2" name="mem_left_track_7"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_left_track_9" hierarchy_level="2">
@@ -2902,7 +2902,7 @@
 				<instance level="2" name="mem_left_track_11"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 			</input_nets>
@@ -3128,7 +3128,7 @@
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="c"/>
+				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -3174,7 +3174,7 @@
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="c"/>
+				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -3266,7 +3266,7 @@
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="c"/>
+				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -3287,7 +3287,7 @@
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="c"/>
+				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
@@ -3341,12 +3341,12 @@
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="c"/>
 			</output_nets>
-			<bitstream path_id="-1">
+			<bitstream path_id="3">
 				<bit memory_port="mem_out[0]" value="0"/>
 				<bit memory_port="mem_out[1]" value="0"/>
-				<bit memory_port="mem_out[2]" value="0"/>
+				<bit memory_port="mem_out[2]" value="1"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_bottom_ipin_2" hierarchy_level="2">
@@ -3382,7 +3382,7 @@
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="c"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
@@ -3403,7 +3403,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="c"/>
+				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
@@ -3541,7 +3541,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="c"/>
+				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
@@ -3616,7 +3616,7 @@
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="c"/>
+				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
 				<path id="0" net_name="unmapped"/>
@@ -3662,7 +3662,7 @@
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="c"/>
+				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
 				<path id="0" net_name="unmapped"/>
@@ -3754,7 +3754,7 @@
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="c"/>
+				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
 				<path id="0" net_name="unmapped"/>
@@ -3775,7 +3775,7 @@
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="c"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
@@ -3845,7 +3845,7 @@
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="c"/>
+				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
@@ -3866,7 +3866,7 @@
 				<instance level="2" name="mem_left_ipin_3"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
@@ -3891,18 +3891,18 @@
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="c"/>
+				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="a"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="2">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
 				<bit memory_port="mem_out[1]" value="0"/>
-				<bit memory_port="mem_out[2]" value="1"/>
+				<bit memory_port="mem_out[2]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_left_ipin_5" hierarchy_level="2">
@@ -3912,7 +3912,7 @@
 				<instance level="2" name="mem_left_ipin_5"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
@@ -4004,7 +4004,7 @@
 				<instance level="2" name="mem_right_ipin_1"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>

openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc

@@ -14,7 +14,7 @@ set_units -time s
 ##################################################
 # Create clock                                    
 ##################################################
-create_clock -name clk[0] -period 1.618133072e-09 -waveform {0 8.09066536e-10} [get_ports {clk[0]}]
+create_clock -name clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10} [get_ports {clk[0]}]
 ##################################################
 # Create programmable clock                       
 ##################################################

openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml

@@ -5,5 +5,5 @@
 <io_mapping>
 	<io name="gfpga_pad_GPIO_PAD[11:11]" net="a" dir="input"/>
 	<io name="gfpga_pad_GPIO_PAD[14:14]" net="b" dir="input"/>
-	<io name="gfpga_pad_GPIO_PAD[12:12]" net="c" dir="output"/>
+	<io name="gfpga_pad_GPIO_PAD[1:1]" net="c" dir="output"/>
 </io_mapping>

openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v

@@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb;
 	initial begin
 		clk[0] <= 1'b0;
 		while(1) begin
-			#0.782782793
+			#0.8625563979
 			clk[0] <= !clk[0];
 		end
 	end
@@ -106,7 +106,7 @@ initial begin
 	$timeformat(-9, 2, "ns", 20);
 	$display("Simulation start");
 // ----- Can be changed by the user for his/her need -------
-	#10.95895958
+	#12.07578945
 	if(nb_error == 0) begin
 		$display("Simulation Succeed");
 	end else begin

openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v

@@ -39,11 +39,11 @@ wire [0:0] clk_fm;
 // ----- End Connect Global ports of FPGA top module -----
 
 // ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
-// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[79] -----
+// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[38] -----
-	assign gfpga_pad_GPIO_PAD_fm[79] = a[0];
+	assign gfpga_pad_GPIO_PAD_fm[38] = a[0];
 
-// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[74] -----
+// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[58] -----
-	assign gfpga_pad_GPIO_PAD_fm[74] = b[0];
+	assign gfpga_pad_GPIO_PAD_fm[58] = b[0];
 
 // ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[17] -----
 	assign c[0] = gfpga_pad_GPIO_PAD_fm[17];
@@ -86,7 +86,6 @@ wire [0:0] clk_fm;
 	assign gfpga_pad_GPIO_PAD_fm[35] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[36] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[37] = 1'b0;
-	assign gfpga_pad_GPIO_PAD_fm[38] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[39] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[40] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[41] = 1'b0;
@@ -106,7 +105,6 @@ wire [0:0] clk_fm;
 	assign gfpga_pad_GPIO_PAD_fm[55] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[56] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[57] = 1'b0;
-	assign gfpga_pad_GPIO_PAD_fm[58] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[59] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[60] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[61] = 1'b0;
@@ -122,10 +120,12 @@ wire [0:0] clk_fm;
 	assign gfpga_pad_GPIO_PAD_fm[71] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[72] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[73] = 1'b0;
+	assign gfpga_pad_GPIO_PAD_fm[74] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[75] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[76] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[77] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[78] = 1'b0;
+	assign gfpga_pad_GPIO_PAD_fm[79] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[80] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[81] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[82] = 1'b0;
@@ -622,10 +622,10 @@ initial begin
 	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
 	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000;
+	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
-	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111;
+	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
-	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01;
+	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10;
+	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}};
@@ -650,14 +650,14 @@ initial begin
 	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b1011;
+	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}};
-	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b0100;
+	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b1}};
+	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}};
-	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b0}};
+	force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.grid_clb_3__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
 	force U0_formal_verification.grid_clb_3__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
 	force U0_formal_verification.grid_clb_3__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
@@ -862,10 +862,10 @@ initial begin
 	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
 	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
+	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000;
-	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
+	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111;
-	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
+	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01;
-	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
+	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10;
 	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}};
@@ -890,14 +890,14 @@ initial begin
 	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}};
+	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b1110;
-	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}};
+	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b0001;
 	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}};
+	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0001;
-	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}};
+	force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1110;
 	force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
 	force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
 	force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
@@ -1406,8 +1406,8 @@ initial begin
 	force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
+	force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_out[0:3] = 4'b0111;
-	force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
+	force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_outb[0:3] = 4'b1000;
 	force U0_formal_verification.sb_1__2_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_1__2_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_1__2_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
@@ -1432,8 +1432,8 @@ initial begin
 	force U0_formal_verification.sb_1__2_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_1__3_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_1__3_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.sb_1__3_.mem_top_track_8.mem_out[0:3] = 4'b0011;
+	force U0_formal_verification.sb_1__3_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
-	force U0_formal_verification.sb_1__3_.mem_top_track_8.mem_outb[0:3] = 4'b1100;
+	force U0_formal_verification.sb_1__3_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_1__3_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_1__3_.mem_top_track_16.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_1__3_.mem_right_track_0.mem_out[0:3] = {4{1'b0}};
@@ -1454,8 +1454,8 @@ initial begin
 	force U0_formal_verification.sb_1__3_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_1__3_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_1__3_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_out[0:3] = 4'b0101;
+	force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_out[0:3] = 4'b0011;
-	force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_outb[0:3] = 4'b1010;
+	force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_outb[0:3] = 4'b1100;
 	force U0_formal_verification.sb_1__4_.mem_right_track_8.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_1__4_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_1__4_.mem_right_track_16.mem_out[0:3] = {4{1'b0}};
@@ -1492,14 +1492,14 @@ initial begin
 	force U0_formal_verification.sb_2__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_2__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_2__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_out[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_2__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_2__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_2__0_.mem_top_track_18.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.sb_2__0_.mem_top_track_18.mem_outb[0:2] = {3{1'b1}};
-	force U0_formal_verification.sb_2__0_.mem_right_track_0.mem_out[0:3] = 4'b0101;
+	force U0_formal_verification.sb_2__0_.mem_right_track_0.mem_out[0:3] = {4{1'b0}};
-	force U0_formal_verification.sb_2__0_.mem_right_track_0.mem_outb[0:3] = 4'b1010;
+	force U0_formal_verification.sb_2__0_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_2__0_.mem_right_track_8.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_2__0_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_2__0_.mem_right_track_16.mem_out[0:3] = {4{1'b0}};
@@ -1516,8 +1516,8 @@ initial begin
 	force U0_formal_verification.sb_2__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_2__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_2__1_.mem_top_track_16.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.sb_2__1_.mem_right_track_0.mem_out[0:3] = 4'b0101;
+	force U0_formal_verification.sb_2__1_.mem_right_track_0.mem_out[0:3] = {4{1'b0}};
-	force U0_formal_verification.sb_2__1_.mem_right_track_0.mem_outb[0:3] = 4'b1010;
+	force U0_formal_verification.sb_2__1_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_2__1_.mem_right_track_8.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_2__1_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_2__1_.mem_right_track_16.mem_out[0:3] = {4{1'b0}};
@@ -1614,8 +1614,8 @@ initial begin
 	force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_out[0:2] = 3'b001;
+	force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}};
-	force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_outb[0:2] = 3'b110;
+	force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.sb_3__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_3__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_3__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
@@ -1636,10 +1636,10 @@ initial begin
 	force U0_formal_verification.sb_3__0_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_3__0_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_3__0_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_out[0:3] = 4'b0100;
+	force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
-	force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_outb[0:3] = 4'b1011;
+	force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_out[0:3] = {4{1'b1}};
+	force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_out[0:3] = 4'b0111;
-	force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b0}};
+	force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_outb[0:3] = 4'b1000;
 	force U0_formal_verification.sb_3__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_3__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_3__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}};
@@ -1680,12 +1680,12 @@ initial begin
 	force U0_formal_verification.sb_3__2_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_3__2_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_3__2_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_out[0:3] = {4{1'b0}};
+	force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_out[0:3] = 4'b0101;
-	force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
+	force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_outb[0:3] = 4'b1010;
 	force U0_formal_verification.sb_3__2_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_3__2_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_out[0:3] = 4'b0110;
+	force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
-	force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_outb[0:3] = 4'b1001;
+	force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_3__3_.mem_top_track_0.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_3__3_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_3__3_.mem_top_track_8.mem_out[0:3] = {4{1'b0}};
@@ -1708,8 +1708,8 @@ initial begin
 	force U0_formal_verification.sb_3__3_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_3__3_.mem_left_track_9.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_3__3_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.sb_3__3_.mem_left_track_17.mem_out[0:3] = 4'b0110;
+	force U0_formal_verification.sb_3__3_.mem_left_track_17.mem_out[0:3] = {4{1'b0}};
-	force U0_formal_verification.sb_3__3_.mem_left_track_17.mem_outb[0:3] = 4'b1001;
+	force U0_formal_verification.sb_3__3_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_3__4_.mem_right_track_0.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_3__4_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_3__4_.mem_right_track_8.mem_out[0:3] = {4{1'b0}};
@@ -1748,8 +1748,8 @@ initial begin
 	force U0_formal_verification.sb_4__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_4__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_out[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_4__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
@@ -1792,8 +1792,8 @@ initial begin
 	force U0_formal_verification.sb_4__1_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_4__1_.mem_left_track_1.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__1_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_out[0:1] = 2'b01;
-	force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_outb[0:1] = 2'b10;
 	force U0_formal_verification.sb_4__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_4__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
@@ -1830,8 +1830,8 @@ initial begin
 	force U0_formal_verification.sb_4__2_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_4__2_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__2_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_out[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__2_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__2_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_4__2_.mem_left_track_13.mem_out[0:1] = {2{1'b0}};
@@ -1852,8 +1852,8 @@ initial begin
 	force U0_formal_verification.sb_4__3_.mem_bottom_track_1.mem_outb[0:3] = {4{1'b1}};
 	force U0_formal_verification.sb_4__3_.mem_bottom_track_9.mem_out[0:3] = {4{1'b0}};
 	force U0_formal_verification.sb_4__3_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}};
-	force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}};
+	force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_out[0:3] = 4'b0101;
-	force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}};
+	force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_outb[0:3] = 4'b1010;
 	force U0_formal_verification.sb_4__3_.mem_left_track_1.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__3_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_4__3_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
@@ -1864,8 +1864,8 @@ initial begin
 	force U0_formal_verification.sb_4__3_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_4__3_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__3_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_out[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_outb[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__3_.mem_left_track_13.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__3_.mem_left_track_13.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_4__3_.mem_left_track_15.mem_out[0:1] = {2{1'b0}};
@@ -1886,8 +1886,8 @@ initial begin
 	force U0_formal_verification.sb_4__4_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_4__4_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__4_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_out[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__4_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_4__4_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_4__4_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
@@ -2092,8 +2092,8 @@ initial begin
 	force U0_formal_verification.cbx_3__0_.mem_top_ipin_6.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cbx_3__0_.mem_top_ipin_7.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cbx_3__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}};
-	force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b1}};
+	force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
-	force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b0}};
+	force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_1.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_1.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
@@ -2110,8 +2110,8 @@ initial begin
 	force U0_formal_verification.cbx_3__2_.mem_bottom_ipin_1.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.cbx_3__2_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cbx_3__2_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
-	force U0_formal_verification.cbx_3__2_.mem_top_ipin_0.mem_out[0:2] = 3'b010;
+	force U0_formal_verification.cbx_3__2_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}};
-	force U0_formal_verification.cbx_3__2_.mem_top_ipin_0.mem_outb[0:2] = 3'b101;
+	force U0_formal_verification.cbx_3__2_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cbx_3__2_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cbx_3__2_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cbx_3__2_.mem_top_ipin_2.mem_out[0:1] = {2{1'b0}};
@@ -2206,8 +2206,8 @@ initial begin
 	force U0_formal_verification.cbx_4__3_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cbx_4__3_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cbx_4__3_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
-	force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_out[0:1] = {2{1'b0}};
+	force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_out[0:1] = 2'b01;
-	force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_outb[0:1] = {2{1'b1}};
+	force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_outb[0:1] = 2'b10;
 	force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
@@ -2412,8 +2412,8 @@ initial begin
 	force U0_formal_verification.cby_3__2_.mem_right_ipin_2.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.cby_3__3_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cby_3__3_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}};
-	force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_out[0:1] = {2{1'b0}};
+	force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_out[0:1] = {2{1'b1}};
-	force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b1}};
+	force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b0}};
 	force U0_formal_verification.cby_3__3_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cby_3__3_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cby_3__3_.mem_right_ipin_1.mem_out[0:1] = {2{1'b0}};

openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit

@@ -222,7 +222,6 @@
 0
 0
 1
-0
 1
 0
 0
@@ -623,6 +622,7 @@
 0
 0
 0
+0
 1
 1
 1
@@ -894,6 +894,8 @@
 0
 0
 0
+1
+1
 0
 0
 0
@@ -906,6 +908,7 @@
 0
 0
 0
+1
 0
 0
 0
@@ -918,6 +921,9 @@
 0
 0
 0
+1
+1
+1
 0
 0
 0
@@ -966,6 +972,7 @@
 0
 0
 0
+1
 0
 0
 0
@@ -976,9 +983,13 @@
 0
 0
 0
+1
 0
+1
 0
+1
 0
+1
 0
 0
 0
@@ -1064,6 +1075,7 @@
 0
 0
 0
+1
 0
 0
 0
@@ -1087,6 +1099,8 @@
 0
 0
 0
+1
+1
 0
 0
 0
@@ -1097,7 +1111,9 @@
 0
 0
 0
+1
 0
+1
 0
 0
 0
@@ -1262,6 +1278,8 @@
 0
 0
 0
+1
+1
 0
 0
 0
@@ -1300,12 +1318,6 @@
 0
 0
 0
-1
-1
-0
-0
-0
-0
 0
 0
 0
@@ -1763,8 +1775,6 @@
 0
 0
 0
-1
-1
 0
 0
 0
@@ -1969,6 +1979,9 @@
 0
 0
 0
+1
+1
+1
 0
 0
 0
@@ -2195,10 +2208,6 @@
 0
 0
 0
-1
-1
-1
-1
 0
 0
 0
@@ -2207,10 +2216,7 @@
 0
 0
 0
-1
-1
 0
-1
 0
 0
 0
@@ -2259,7 +2265,6 @@
 0
 0
 0
-1
 0
 0
 0
@@ -2270,13 +2275,9 @@
 0
 0
 0
-1
 0
-1
 0
-1
 0
-1
 0
 0
 0
@@ -2349,7 +2350,6 @@
 0
 0
 0
-1
 0
 0
 0
@@ -2360,8 +2360,6 @@
 0
 0
 0
-1
-1
 0
 0
 0
@@ -2369,7 +2367,9 @@
 0
 0
 0
+1
 0
+1
 0
 0
 0
@@ -2600,6 +2600,8 @@
 0
 0
 0
+1
+1
 0
 0
 0
@@ -2831,6 +2833,7 @@
 0
 0
 0
+1
 0
 0
 0
@@ -3022,9 +3025,6 @@
 0
 0
 0
-1
-1
-1
 0
 0
 0
@@ -3072,7 +3072,6 @@
 1
 1
 1
-1
 0
 0
 0
@@ -3269,9 +3268,10 @@
 0
 0
 0
-1
 0
-1
+0
+0
+0
 0
 0
 0
@@ -3933,8 +3933,8 @@
 0
 0
 0
-0
+1
-0
+1
 0
 0
 0
@@ -3983,7 +3983,6 @@
 0
 0
 0
-1
 0
 0
 0
@@ -4016,7 +4015,8 @@
 0
 0
 0
-1
+0
+0
 0
 0
 1
@@ -4079,17 +4079,17 @@
 0
 0
 0
-1
 0
-1
 0
 0
 0
 0
 0
 0
-1
+0
-1
+0
+0
+0
 0
 0
 0

openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml

@@ -448,9 +448,9 @@
 		</bit>
 		<bit id="3989" value="1" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[3]">
 		</bit>
-		<bit id="3988" value="0" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[2]">
+		<bit id="3988" value="1" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[2]">
 		</bit>
-		<bit id="3987" value="1" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[1]">
+		<bit id="3987" value="0" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[1]">
 		</bit>
 		<bit id="3986" value="0" path="fpga_top.sb_1__4_.mem_right_track_0.mem_out[0]">
 		</bit>
@@ -1792,9 +1792,9 @@
 		</bit>
 		<bit id="3317" value="0" path="fpga_top.sb_4__4_.mem_bottom_track_15.mem_out[0]">
 		</bit>
-		<bit id="3316" value="0" path="fpga_top.sb_4__4_.mem_bottom_track_13.mem_out[1]">
+		<bit id="3316" value="1" path="fpga_top.sb_4__4_.mem_bottom_track_13.mem_out[1]">
 		</bit>
-		<bit id="3315" value="0" path="fpga_top.sb_4__4_.mem_bottom_track_13.mem_out[0]">
+		<bit id="3315" value="1" path="fpga_top.sb_4__4_.mem_bottom_track_13.mem_out[0]">
 		</bit>
 		<bit id="3314" value="0" path="fpga_top.sb_4__4_.mem_bottom_track_11.mem_out[1]">
 		</bit>
@@ -1820,7 +1820,7 @@
 		</bit>
 		<bit id="3303" value="0" path="fpga_top.sb_4__4_.mem_bottom_track_1.mem_out[0]">
 		</bit>
-		<bit id="3302" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
+		<bit id="3302" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
 		</bit>
 		<bit id="3301" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]">
 		</bit>
@@ -1846,11 +1846,11 @@
 		</bit>
 		<bit id="3290" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
 		</bit>
-		<bit id="3289" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
+		<bit id="3289" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
 		</bit>
-		<bit id="3288" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
+		<bit id="3288" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
 		</bit>
-		<bit id="3287" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
+		<bit id="3287" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
 		</bit>
 		<bit id="3286" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[3]">
 		</bit>
@@ -1948,7 +1948,7 @@
 		</bit>
 		<bit id="3239" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0]">
 		</bit>
-		<bit id="3238" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
+		<bit id="3238" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
 		</bit>
 		<bit id="3237" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0]">
 		</bit>
@@ -1970,19 +1970,19 @@
 		</bit>
 		<bit id="3228" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[7]">
 		</bit>
-		<bit id="3227" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
+		<bit id="3227" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
 		</bit>
 		<bit id="3226" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[5]">
 		</bit>
-		<bit id="3225" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
+		<bit id="3225" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
 		</bit>
 		<bit id="3224" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[3]">
 		</bit>
-		<bit id="3223" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
+		<bit id="3223" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
 		</bit>
 		<bit id="3222" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[1]">
 		</bit>
-		<bit id="3221" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
+		<bit id="3221" value="1" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
 		</bit>
 		<bit id="3220" value="0" path="fpga_top.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
 		</bit>
@@ -2154,7 +2154,7 @@
 		</bit>
 		<bit id="3136" value="0" path="fpga_top.cby_4__3_.mem_left_ipin_0.mem_out[0]">
 		</bit>
-		<bit id="3135" value="0" path="fpga_top.cbx_4__3_.mem_top_ipin_2.mem_out[1]">
+		<bit id="3135" value="1" path="fpga_top.cbx_4__3_.mem_top_ipin_2.mem_out[1]">
 		</bit>
 		<bit id="3134" value="0" path="fpga_top.cbx_4__3_.mem_top_ipin_2.mem_out[0]">
 		</bit>
@@ -2202,9 +2202,9 @@
 		</bit>
 		<bit id="3112" value="0" path="fpga_top.sb_4__3_.mem_left_track_13.mem_out[0]">
 		</bit>
-		<bit id="3111" value="0" path="fpga_top.sb_4__3_.mem_left_track_11.mem_out[1]">
+		<bit id="3111" value="1" path="fpga_top.sb_4__3_.mem_left_track_11.mem_out[1]">
 		</bit>
-		<bit id="3110" value="0" path="fpga_top.sb_4__3_.mem_left_track_11.mem_out[0]">
+		<bit id="3110" value="1" path="fpga_top.sb_4__3_.mem_left_track_11.mem_out[0]">
 		</bit>
 		<bit id="3109" value="0" path="fpga_top.sb_4__3_.mem_left_track_9.mem_out[1]">
 		</bit>
@@ -2226,11 +2226,11 @@
 		</bit>
 		<bit id="3100" value="0" path="fpga_top.sb_4__3_.mem_left_track_1.mem_out[0]">
 		</bit>
-		<bit id="3099" value="0" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[3]">
+		<bit id="3099" value="1" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[3]">
 		</bit>
 		<bit id="3098" value="0" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[2]">
 		</bit>
-		<bit id="3097" value="0" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[1]">
+		<bit id="3097" value="1" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[1]">
 		</bit>
 		<bit id="3096" value="0" path="fpga_top.sb_4__3_.mem_bottom_track_17.mem_out[0]">
 		</bit>
@@ -2560,9 +2560,9 @@
 		</bit>
 		<bit id="2933" value="0" path="fpga_top.cby_3__3_.mem_right_ipin_0.mem_out[0]">
 		</bit>
-		<bit id="2932" value="0" path="fpga_top.cby_3__3_.mem_left_ipin_1.mem_out[1]">
+		<bit id="2932" value="1" path="fpga_top.cby_3__3_.mem_left_ipin_1.mem_out[1]">
 		</bit>
-		<bit id="2931" value="0" path="fpga_top.cby_3__3_.mem_left_ipin_1.mem_out[0]">
+		<bit id="2931" value="1" path="fpga_top.cby_3__3_.mem_left_ipin_1.mem_out[0]">
 		</bit>
 		<bit id="2930" value="0" path="fpga_top.cby_3__3_.mem_left_ipin_0.mem_out[2]">
 		</bit>
@@ -2604,9 +2604,9 @@
 		</bit>
 		<bit id="2911" value="0" path="fpga_top.sb_3__3_.mem_left_track_17.mem_out[3]">
 		</bit>
-		<bit id="2910" value="1" path="fpga_top.sb_3__3_.mem_left_track_17.mem_out[2]">
+		<bit id="2910" value="0" path="fpga_top.sb_3__3_.mem_left_track_17.mem_out[2]">
 		</bit>
-		<bit id="2909" value="1" path="fpga_top.sb_3__3_.mem_left_track_17.mem_out[1]">
+		<bit id="2909" value="0" path="fpga_top.sb_3__3_.mem_left_track_17.mem_out[1]">
 		</bit>
 		<bit id="2908" value="0" path="fpga_top.sb_3__3_.mem_left_track_17.mem_out[0]">
 		</bit>
@@ -3530,9 +3530,9 @@
 		</bit>
 		<bit id="2448" value="0" path="fpga_top.sb_1__3_.mem_top_track_16.mem_out[0]">
 		</bit>
-		<bit id="2447" value="1" path="fpga_top.sb_1__3_.mem_top_track_8.mem_out[3]">
+		<bit id="2447" value="0" path="fpga_top.sb_1__3_.mem_top_track_8.mem_out[3]">
 		</bit>
-		<bit id="2446" value="1" path="fpga_top.sb_1__3_.mem_top_track_8.mem_out[2]">
+		<bit id="2446" value="0" path="fpga_top.sb_1__3_.mem_top_track_8.mem_out[2]">
 		</bit>
 		<bit id="2445" value="0" path="fpga_top.sb_1__3_.mem_top_track_8.mem_out[1]">
 		</bit>
@@ -3962,11 +3962,11 @@
 		</bit>
 		<bit id="2232" value="0" path="fpga_top.sb_1__2_.mem_top_track_8.mem_out[0]">
 		</bit>
-		<bit id="2231" value="0" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[3]">
+		<bit id="2231" value="1" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[3]">
 		</bit>
-		<bit id="2230" value="0" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[2]">
+		<bit id="2230" value="1" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[2]">
 		</bit>
-		<bit id="2229" value="0" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[1]">
+		<bit id="2229" value="1" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[1]">
 		</bit>
 		<bit id="2228" value="0" path="fpga_top.sb_1__2_.mem_top_track_0.mem_out[0]">
 		</bit>
@@ -4394,13 +4394,13 @@
 		</bit>
 		<bit id="2016" value="0" path="fpga_top.sb_2__2_.mem_top_track_0.mem_out[0]">
 		</bit>
-		<bit id="2015" value="1" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
+		<bit id="2015" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
 		</bit>
-		<bit id="2014" value="1" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]">
+		<bit id="2014" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]">
 		</bit>
-		<bit id="2013" value="1" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
+		<bit id="2013" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
 		</bit>
-		<bit id="2012" value="1" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
+		<bit id="2012" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
 		</bit>
 		<bit id="2011" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[3]">
 		</bit>
@@ -4418,13 +4418,13 @@
 		</bit>
 		<bit id="2004" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0]">
 		</bit>
-		<bit id="2003" value="1" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
+		<bit id="2003" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
 		</bit>
-		<bit id="2002" value="1" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
+		<bit id="2002" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
 		</bit>
 		<bit id="2001" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
 		</bit>
-		<bit id="2000" value="1" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
+		<bit id="2000" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
 		</bit>
 		<bit id="1999" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[3]">
 		</bit>
@@ -4522,7 +4522,7 @@
 		</bit>
 		<bit id="1952" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0]">
 		</bit>
-		<bit id="1951" value="1" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
+		<bit id="1951" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
 		</bit>
 		<bit id="1950" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0]">
 		</bit>
@@ -4544,19 +4544,19 @@
 		</bit>
 		<bit id="1941" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[7]">
 		</bit>
-		<bit id="1940" value="1" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
+		<bit id="1940" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[6]">
 		</bit>
 		<bit id="1939" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[5]">
 		</bit>
-		<bit id="1938" value="1" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
+		<bit id="1938" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[4]">
 		</bit>
 		<bit id="1937" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[3]">
 		</bit>
-		<bit id="1936" value="1" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
+		<bit id="1936" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[2]">
 		</bit>
 		<bit id="1935" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[1]">
 		</bit>
-		<bit id="1934" value="1" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
+		<bit id="1934" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0]">
 		</bit>
 		<bit id="1933" value="0" path="fpga_top.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[1]">
 		</bit>
@@ -4702,7 +4702,7 @@
 		</bit>
 		<bit id="1862" value="0" path="fpga_top.cbx_3__2_.mem_top_ipin_0.mem_out[2]">
 		</bit>
-		<bit id="1861" value="1" path="fpga_top.cbx_3__2_.mem_top_ipin_0.mem_out[1]">
+		<bit id="1861" value="0" path="fpga_top.cbx_3__2_.mem_top_ipin_0.mem_out[1]">
 		</bit>
 		<bit id="1860" value="0" path="fpga_top.cbx_3__2_.mem_top_ipin_0.mem_out[0]">
 		</bit>
@@ -4724,9 +4724,9 @@
 		</bit>
 		<bit id="1851" value="0" path="fpga_top.sb_3__2_.mem_left_track_17.mem_out[3]">
 		</bit>
-		<bit id="1850" value="1" path="fpga_top.sb_3__2_.mem_left_track_17.mem_out[2]">
+		<bit id="1850" value="0" path="fpga_top.sb_3__2_.mem_left_track_17.mem_out[2]">
 		</bit>
-		<bit id="1849" value="1" path="fpga_top.sb_3__2_.mem_left_track_17.mem_out[1]">
+		<bit id="1849" value="0" path="fpga_top.sb_3__2_.mem_left_track_17.mem_out[1]">
 		</bit>
 		<bit id="1848" value="0" path="fpga_top.sb_3__2_.mem_left_track_17.mem_out[0]">
 		</bit>
@@ -4738,11 +4738,11 @@
 		</bit>
 		<bit id="1844" value="0" path="fpga_top.sb_3__2_.mem_left_track_9.mem_out[0]">
 		</bit>
-		<bit id="1843" value="0" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[3]">
+		<bit id="1843" value="1" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[3]">
 		</bit>
 		<bit id="1842" value="0" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[2]">
 		</bit>
-		<bit id="1841" value="0" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[1]">
+		<bit id="1841" value="1" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[1]">
 		</bit>
 		<bit id="1840" value="0" path="fpga_top.sb_3__2_.mem_left_track_1.mem_out[0]">
 		</bit>
@@ -5204,9 +5204,9 @@
 		</bit>
 		<bit id="1611" value="0" path="fpga_top.sb_4__2_.mem_left_track_11.mem_out[0]">
 		</bit>
-		<bit id="1610" value="0" path="fpga_top.sb_4__2_.mem_left_track_9.mem_out[1]">
+		<bit id="1610" value="1" path="fpga_top.sb_4__2_.mem_left_track_9.mem_out[1]">
 		</bit>
-		<bit id="1609" value="0" path="fpga_top.sb_4__2_.mem_left_track_9.mem_out[0]">
+		<bit id="1609" value="1" path="fpga_top.sb_4__2_.mem_left_track_9.mem_out[0]">
 		</bit>
 		<bit id="1608" value="0" path="fpga_top.sb_4__2_.mem_left_track_7.mem_out[1]">
 		</bit>
@@ -5670,7 +5670,7 @@
 		</bit>
 		<bit id="1378" value="0" path="fpga_top.sb_4__1_.mem_left_track_5.mem_out[0]">
 		</bit>
-		<bit id="1377" value="0" path="fpga_top.sb_4__1_.mem_left_track_3.mem_out[1]">
+		<bit id="1377" value="1" path="fpga_top.sb_4__1_.mem_left_track_3.mem_out[1]">
 		</bit>
 		<bit id="1376" value="0" path="fpga_top.sb_4__1_.mem_left_track_3.mem_out[0]">
 		</bit>
@@ -6048,11 +6048,11 @@
 		</bit>
 		<bit id="1189" value="0" path="fpga_top.cbx_3__1_.mem_bottom_ipin_1.mem_out[0]">
 		</bit>
-		<bit id="1188" value="1" path="fpga_top.cbx_3__1_.mem_bottom_ipin_0.mem_out[2]">
+		<bit id="1188" value="0" path="fpga_top.cbx_3__1_.mem_bottom_ipin_0.mem_out[2]">
 		</bit>
-		<bit id="1187" value="1" path="fpga_top.cbx_3__1_.mem_bottom_ipin_0.mem_out[1]">
+		<bit id="1187" value="0" path="fpga_top.cbx_3__1_.mem_bottom_ipin_0.mem_out[1]">
 		</bit>
-		<bit id="1186" value="1" path="fpga_top.cbx_3__1_.mem_bottom_ipin_0.mem_out[0]">
+		<bit id="1186" value="0" path="fpga_top.cbx_3__1_.mem_bottom_ipin_0.mem_out[0]">
 		</bit>
 		<bit id="1185" value="0" path="fpga_top.sb_3__1_.mem_left_track_17.mem_out[3]">
 		</bit>
@@ -6148,7 +6148,7 @@
 		</bit>
 		<bit id="1139" value="1" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[1]">
 		</bit>
-		<bit id="1138" value="1" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[0]">
+		<bit id="1138" value="0" path="fpga_top.sb_3__1_.mem_top_track_0.mem_out[0]">
 		</bit>
 		<bit id="1137" value="0" path="fpga_top.grid_clb_2__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[3]">
 		</bit>
@@ -6542,11 +6542,11 @@
 		</bit>
 		<bit id="942" value="0" path="fpga_top.sb_2__1_.mem_right_track_8.mem_out[0]">
 		</bit>
-		<bit id="941" value="1" path="fpga_top.sb_2__1_.mem_right_track_0.mem_out[3]">
+		<bit id="941" value="0" path="fpga_top.sb_2__1_.mem_right_track_0.mem_out[3]">
 		</bit>
 		<bit id="940" value="0" path="fpga_top.sb_2__1_.mem_right_track_0.mem_out[2]">
 		</bit>
-		<bit id="939" value="1" path="fpga_top.sb_2__1_.mem_right_track_0.mem_out[1]">
+		<bit id="939" value="0" path="fpga_top.sb_2__1_.mem_right_track_0.mem_out[1]">
 		</bit>
 		<bit id="938" value="0" path="fpga_top.sb_2__1_.mem_right_track_0.mem_out[0]">
 		</bit>
@@ -7870,9 +7870,9 @@
 		</bit>
 		<bit id="278" value="0" path="fpga_top.sb_4__0_.mem_top_track_8.mem_out[0]">
 		</bit>
-		<bit id="277" value="0" path="fpga_top.sb_4__0_.mem_top_track_6.mem_out[1]">
+		<bit id="277" value="1" path="fpga_top.sb_4__0_.mem_top_track_6.mem_out[1]">
 		</bit>
-		<bit id="276" value="0" path="fpga_top.sb_4__0_.mem_top_track_6.mem_out[0]">
+		<bit id="276" value="1" path="fpga_top.sb_4__0_.mem_top_track_6.mem_out[0]">
 		</bit>
 		<bit id="275" value="0" path="fpga_top.sb_4__0_.mem_top_track_4.mem_out[1]">
 		</bit>
@@ -7970,7 +7970,7 @@
 		</bit>
 		<bit id="228" value="0" path="fpga_top.sb_3__0_.mem_left_track_17.mem_out[2]">
 		</bit>
-		<bit id="227" value="1" path="fpga_top.sb_3__0_.mem_left_track_17.mem_out[1]">
+		<bit id="227" value="0" path="fpga_top.sb_3__0_.mem_left_track_17.mem_out[1]">
 		</bit>
 		<bit id="226" value="0" path="fpga_top.sb_3__0_.mem_left_track_17.mem_out[0]">
 		</bit>
@@ -8036,7 +8036,7 @@
 		</bit>
 		<bit id="195" value="0" path="fpga_top.sb_3__0_.mem_top_track_2.mem_out[0]">
 		</bit>
-		<bit id="194" value="1" path="fpga_top.sb_3__0_.mem_top_track_0.mem_out[2]">
+		<bit id="194" value="0" path="fpga_top.sb_3__0_.mem_top_track_0.mem_out[2]">
 		</bit>
 		<bit id="193" value="0" path="fpga_top.sb_3__0_.mem_top_track_0.mem_out[1]">
 		</bit>
@@ -8162,11 +8162,11 @@
 		</bit>
 		<bit id="132" value="0" path="fpga_top.sb_2__0_.mem_right_track_8.mem_out[0]">
 		</bit>
-		<bit id="131" value="1" path="fpga_top.sb_2__0_.mem_right_track_0.mem_out[3]">
+		<bit id="131" value="0" path="fpga_top.sb_2__0_.mem_right_track_0.mem_out[3]">
 		</bit>
 		<bit id="130" value="0" path="fpga_top.sb_2__0_.mem_right_track_0.mem_out[2]">
 		</bit>
-		<bit id="129" value="1" path="fpga_top.sb_2__0_.mem_right_track_0.mem_out[1]">
+		<bit id="129" value="0" path="fpga_top.sb_2__0_.mem_right_track_0.mem_out[1]">
 		</bit>
 		<bit id="128" value="0" path="fpga_top.sb_2__0_.mem_right_track_0.mem_out[0]">
 		</bit>
@@ -8180,9 +8180,9 @@
 		</bit>
 		<bit id="123" value="0" path="fpga_top.sb_2__0_.mem_top_track_16.mem_out[0]">
 		</bit>
-		<bit id="122" value="1" path="fpga_top.sb_2__0_.mem_top_track_10.mem_out[1]">
+		<bit id="122" value="0" path="fpga_top.sb_2__0_.mem_top_track_10.mem_out[1]">
 		</bit>
-		<bit id="121" value="1" path="fpga_top.sb_2__0_.mem_top_track_10.mem_out[0]">
+		<bit id="121" value="0" path="fpga_top.sb_2__0_.mem_top_track_10.mem_out[0]">
 		</bit>
 		<bit id="120" value="0" path="fpga_top.sb_2__0_.mem_top_track_8.mem_out[1]">
 		</bit>

openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc

@@ -14,7 +14,7 @@ set_units -time s
 ##################################################
 # Create clock                                    
 ##################################################
-create_clock -name clk[0] -period 1.565565566e-09 -waveform {0 7.82782783e-10} [get_ports {clk[0]}]
+create_clock -name clk[0] -period 1.725112719e-09 -waveform {0 8.625563597e-10} [get_ports {clk[0]}]
 ##################################################
 # Create programmable clock                       
 ##################################################

openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/pin_mapping.xml

@@ -3,7 +3,7 @@
 -->
 
 <io_mapping>
-	<io name="gfpga_pad_GPIO_PAD[79:79]" net="a" dir="input"/>
+	<io name="gfpga_pad_GPIO_PAD[38:38]" net="a" dir="input"/>
-	<io name="gfpga_pad_GPIO_PAD[74:74]" net="b" dir="input"/>
+	<io name="gfpga_pad_GPIO_PAD[58:58]" net="b" dir="input"/>
 	<io name="gfpga_pad_GPIO_PAD[17:17]" net="c" dir="output"/>
 </io_mapping>

openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v

@@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb;
 	initial begin
 		clk[0] <= 1'b0;
 		while(1) begin
-			#0.809066534
+			#0.4880859554
 			clk[0] <= !clk[0];
 		end
 	end
@@ -106,7 +106,7 @@ initial begin
 	$timeformat(-9, 2, "ns", 20);
 	$display("Simulation start");
 // ----- Can be changed by the user for his/her need -------
-	#11.32693195
+	#6.833203316
 	if(nb_error == 0) begin
 		$display("Simulation Succeed");
 	end else begin

openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc

@@ -9,20 +9,19 @@
 ##################################################
 # Create clock                                    
 ##################################################
-create_clock clk[0] -period 1.618133072e-09 -waveform {0 8.09066536e-10}
+create_clock clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10}
 
 ##################################################
 # Create input and output delays for used I/Os    
 ##################################################
-set_input_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[11]
+set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[11]
-set_input_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[14]
+set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[14]
-set_output_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[12]
+set_output_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[1]
 
 ##################################################
 # Disable timing for unused I/Os    
 ##################################################
 set_disable_timing gfpga_pad_GPIO_PAD[0]
-set_disable_timing gfpga_pad_GPIO_PAD[1]
 set_disable_timing gfpga_pad_GPIO_PAD[2]
 set_disable_timing gfpga_pad_GPIO_PAD[3]
 set_disable_timing gfpga_pad_GPIO_PAD[4]
@@ -32,6 +31,7 @@ set_disable_timing gfpga_pad_GPIO_PAD[7]
 set_disable_timing gfpga_pad_GPIO_PAD[8]
 set_disable_timing gfpga_pad_GPIO_PAD[9]
 set_disable_timing gfpga_pad_GPIO_PAD[10]
+set_disable_timing gfpga_pad_GPIO_PAD[12]
 set_disable_timing gfpga_pad_GPIO_PAD[13]
 set_disable_timing gfpga_pad_GPIO_PAD[15]
 set_disable_timing gfpga_pad_GPIO_PAD[16]
@@ -156,9 +156,11 @@ set_disable_timing cbx_1__0_/chanx_left_in[7]
 set_disable_timing cbx_1__0_/chanx_right_in[7]
 set_disable_timing cbx_1__0_/chanx_left_in[8]
 set_disable_timing cbx_1__0_/chanx_right_in[8]
+set_disable_timing cbx_1__0_/chanx_left_in[9]
 set_disable_timing cbx_1__0_/chanx_right_in[9]
 set_disable_timing cbx_1__0_/chanx_left_in[10]
 set_disable_timing cbx_1__0_/chanx_right_in[10]
+set_disable_timing cbx_1__0_/chanx_left_in[11]
 set_disable_timing cbx_1__0_/chanx_right_in[11]
 set_disable_timing cbx_1__0_/chanx_left_in[12]
 set_disable_timing cbx_1__0_/chanx_right_in[12]
@@ -180,9 +182,11 @@ set_disable_timing cbx_1__0_/chanx_left_out[7]
 set_disable_timing cbx_1__0_/chanx_right_out[7]
 set_disable_timing cbx_1__0_/chanx_left_out[8]
 set_disable_timing cbx_1__0_/chanx_right_out[8]
+set_disable_timing cbx_1__0_/chanx_left_out[9]
 set_disable_timing cbx_1__0_/chanx_right_out[9]
 set_disable_timing cbx_1__0_/chanx_left_out[10]
 set_disable_timing cbx_1__0_/chanx_right_out[10]
+set_disable_timing cbx_1__0_/chanx_left_out[11]
 set_disable_timing cbx_1__0_/chanx_right_out[11]
 set_disable_timing cbx_1__0_/chanx_left_out[12]
 set_disable_timing cbx_1__0_/chanx_right_out[12]
@@ -272,6 +276,7 @@ set_disable_timing cbx_1__1_/chanx_left_in[1]
 set_disable_timing cbx_1__1_/chanx_left_in[2]
 set_disable_timing cbx_1__1_/chanx_right_in[2]
 set_disable_timing cbx_1__1_/chanx_left_in[3]
+set_disable_timing cbx_1__1_/chanx_right_in[3]
 set_disable_timing cbx_1__1_/chanx_left_in[4]
 set_disable_timing cbx_1__1_/chanx_right_in[4]
 set_disable_timing cbx_1__1_/chanx_left_in[5]
@@ -296,6 +301,7 @@ set_disable_timing cbx_1__1_/chanx_left_out[1]
 set_disable_timing cbx_1__1_/chanx_left_out[2]
 set_disable_timing cbx_1__1_/chanx_right_out[2]
 set_disable_timing cbx_1__1_/chanx_left_out[3]
+set_disable_timing cbx_1__1_/chanx_right_out[3]
 set_disable_timing cbx_1__1_/chanx_left_out[4]
 set_disable_timing cbx_1__1_/chanx_right_out[4]
 set_disable_timing cbx_1__1_/chanx_left_out[5]
@@ -315,7 +321,6 @@ set_disable_timing cbx_1__1_/chanx_right_out[11]
 set_disable_timing cbx_1__1_/chanx_left_out[12]
 set_disable_timing cbx_1__1_/chanx_right_out[12]
 set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0]
-set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0]
 set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0]
 set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0]
 set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0]
@@ -334,7 +339,6 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[0]
 set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[3]
 set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[1]
 set_disable_timing cbx_1__1_/mux_top_ipin_0/in[1]
-set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[2]
 set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[0]
 set_disable_timing cbx_1__1_/mux_top_ipin_0/in[0]
 set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[3]
@@ -411,9 +415,11 @@ set_disable_timing cby_0__1_/chany_top_in[6]
 set_disable_timing cby_0__1_/chany_bottom_in[7]
 set_disable_timing cby_0__1_/chany_top_in[7]
 set_disable_timing cby_0__1_/chany_bottom_in[8]
+set_disable_timing cby_0__1_/chany_top_in[8]
 set_disable_timing cby_0__1_/chany_bottom_in[9]
 set_disable_timing cby_0__1_/chany_top_in[9]
 set_disable_timing cby_0__1_/chany_bottom_in[10]
+set_disable_timing cby_0__1_/chany_top_in[10]
 set_disable_timing cby_0__1_/chany_bottom_in[11]
 set_disable_timing cby_0__1_/chany_top_in[11]
 set_disable_timing cby_0__1_/chany_bottom_in[12]
@@ -435,9 +441,11 @@ set_disable_timing cby_0__1_/chany_top_out[6]
 set_disable_timing cby_0__1_/chany_bottom_out[7]
 set_disable_timing cby_0__1_/chany_top_out[7]
 set_disable_timing cby_0__1_/chany_bottom_out[8]
+set_disable_timing cby_0__1_/chany_top_out[8]
 set_disable_timing cby_0__1_/chany_bottom_out[9]
 set_disable_timing cby_0__1_/chany_top_out[9]
 set_disable_timing cby_0__1_/chany_bottom_out[10]
+set_disable_timing cby_0__1_/chany_top_out[10]
 set_disable_timing cby_0__1_/chany_bottom_out[11]
 set_disable_timing cby_0__1_/chany_top_out[11]
 set_disable_timing cby_0__1_/chany_bottom_out[12]
@@ -518,9 +526,11 @@ set_disable_timing cby_0__1_/mux_right_ipin_4/in[4]
 set_disable_timing cby_1__1_/chany_top_in[0]
 set_disable_timing cby_1__1_/chany_bottom_in[1]
 set_disable_timing cby_1__1_/chany_top_in[1]
+set_disable_timing cby_1__1_/chany_bottom_in[2]
 set_disable_timing cby_1__1_/chany_top_in[2]
 set_disable_timing cby_1__1_/chany_bottom_in[3]
 set_disable_timing cby_1__1_/chany_top_in[3]
+set_disable_timing cby_1__1_/chany_bottom_in[4]
 set_disable_timing cby_1__1_/chany_top_in[4]
 set_disable_timing cby_1__1_/chany_bottom_in[5]
 set_disable_timing cby_1__1_/chany_top_in[5]
@@ -539,9 +549,11 @@ set_disable_timing cby_1__1_/chany_top_in[12]
 set_disable_timing cby_1__1_/chany_top_out[0]
 set_disable_timing cby_1__1_/chany_bottom_out[1]
 set_disable_timing cby_1__1_/chany_top_out[1]
+set_disable_timing cby_1__1_/chany_bottom_out[2]
 set_disable_timing cby_1__1_/chany_top_out[2]
 set_disable_timing cby_1__1_/chany_bottom_out[3]
 set_disable_timing cby_1__1_/chany_top_out[3]
+set_disable_timing cby_1__1_/chany_bottom_out[4]
 set_disable_timing cby_1__1_/chany_top_out[4]
 set_disable_timing cby_1__1_/chany_bottom_out[5]
 set_disable_timing cby_1__1_/chany_top_out[5]
@@ -561,6 +573,7 @@ set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_out
 set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0]
 set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0]
 set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0]
+set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0]
 set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0]
 set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0]
 set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0]
@@ -589,6 +602,7 @@ set_disable_timing cby_1__1_/mux_right_ipin_2/in[1]
 set_disable_timing cby_1__1_/mux_left_ipin_3/in[2]
 set_disable_timing cby_1__1_/mux_left_ipin_4/in[0]
 set_disable_timing cby_1__1_/mux_right_ipin_2/in[0]
+set_disable_timing cby_1__1_/mux_left_ipin_4/in[3]
 set_disable_timing cby_1__1_/mux_left_ipin_5/in[1]
 set_disable_timing cby_1__1_/mux_left_ipin_4/in[2]
 set_disable_timing cby_1__1_/mux_left_ipin_5/in[0]
@@ -648,9 +662,11 @@ set_disable_timing sb_0__0_/chany_top_in[6]
 set_disable_timing sb_0__0_/chany_top_out[7]
 set_disable_timing sb_0__0_/chany_top_in[7]
 set_disable_timing sb_0__0_/chany_top_out[8]
+set_disable_timing sb_0__0_/chany_top_in[8]
 set_disable_timing sb_0__0_/chany_top_out[9]
 set_disable_timing sb_0__0_/chany_top_in[9]
 set_disable_timing sb_0__0_/chany_top_out[10]
+set_disable_timing sb_0__0_/chany_top_in[10]
 set_disable_timing sb_0__0_/chany_top_out[11]
 set_disable_timing sb_0__0_/chany_top_in[11]
 set_disable_timing sb_0__0_/chany_top_out[12]
@@ -673,9 +689,11 @@ set_disable_timing sb_0__0_/chanx_right_out[7]
 set_disable_timing sb_0__0_/chanx_right_in[7]
 set_disable_timing sb_0__0_/chanx_right_out[8]
 set_disable_timing sb_0__0_/chanx_right_in[8]
+set_disable_timing sb_0__0_/chanx_right_out[9]
 set_disable_timing sb_0__0_/chanx_right_in[9]
 set_disable_timing sb_0__0_/chanx_right_out[10]
 set_disable_timing sb_0__0_/chanx_right_in[10]
+set_disable_timing sb_0__0_/chanx_right_out[11]
 set_disable_timing sb_0__0_/chanx_right_in[11]
 set_disable_timing sb_0__0_/chanx_right_out[12]
 set_disable_timing sb_0__0_/chanx_right_in[12]
@@ -757,7 +775,9 @@ set_disable_timing sb_0__0_/mux_right_track_10/in[0]
 set_disable_timing sb_0__0_/mux_right_track_12/in[0]
 set_disable_timing sb_0__0_/mux_right_track_14/in[0]
 set_disable_timing sb_0__0_/mux_right_track_16/in[0]
+set_disable_timing sb_0__0_/mux_right_track_18/in[0]
 set_disable_timing sb_0__0_/mux_right_track_20/in[0]
+set_disable_timing sb_0__0_/mux_right_track_22/in[0]
 set_disable_timing sb_0__0_/mux_right_track_24/in[0]
 set_disable_timing sb_0__0_/mux_right_track_0/in[0]
 set_disable_timing sb_0__0_/mux_top_track_24/in[2]
@@ -782,6 +802,7 @@ set_disable_timing sb_0__1_/chanx_right_out[1]
 set_disable_timing sb_0__1_/chanx_right_out[2]
 set_disable_timing sb_0__1_/chanx_right_in[2]
 set_disable_timing sb_0__1_/chanx_right_out[3]
+set_disable_timing sb_0__1_/chanx_right_in[3]
 set_disable_timing sb_0__1_/chanx_right_out[4]
 set_disable_timing sb_0__1_/chanx_right_in[4]
 set_disable_timing sb_0__1_/chanx_right_out[5]
@@ -817,9 +838,11 @@ set_disable_timing sb_0__1_/chany_bottom_out[6]
 set_disable_timing sb_0__1_/chany_bottom_in[7]
 set_disable_timing sb_0__1_/chany_bottom_out[7]
 set_disable_timing sb_0__1_/chany_bottom_in[8]
+set_disable_timing sb_0__1_/chany_bottom_out[8]
 set_disable_timing sb_0__1_/chany_bottom_in[9]
 set_disable_timing sb_0__1_/chany_bottom_out[9]
 set_disable_timing sb_0__1_/chany_bottom_in[10]
+set_disable_timing sb_0__1_/chany_bottom_out[10]
 set_disable_timing sb_0__1_/chany_bottom_in[11]
 set_disable_timing sb_0__1_/chany_bottom_out[11]
 set_disable_timing sb_0__1_/chany_bottom_in[12]
@@ -893,7 +916,9 @@ set_disable_timing sb_0__1_/mux_bottom_track_3/in[3]
 set_disable_timing sb_0__1_/mux_bottom_track_15/in[3]
 set_disable_timing sb_0__1_/mux_bottom_track_17/in[2]
 set_disable_timing sb_0__1_/mux_bottom_track_23/in[0]
+set_disable_timing sb_0__1_/mux_bottom_track_21/in[0]
 set_disable_timing sb_0__1_/mux_bottom_track_19/in[0]
+set_disable_timing sb_0__1_/mux_bottom_track_17/in[0]
 set_disable_timing sb_0__1_/mux_bottom_track_15/in[0]
 set_disable_timing sb_0__1_/mux_bottom_track_13/in[0]
 set_disable_timing sb_0__1_/mux_bottom_track_11/in[0]
@@ -922,9 +947,11 @@ set_disable_timing sb_0__1_/mux_right_track_24/in[2]
 set_disable_timing sb_1__0_/chany_top_in[0]
 set_disable_timing sb_1__0_/chany_top_out[1]
 set_disable_timing sb_1__0_/chany_top_in[1]
+set_disable_timing sb_1__0_/chany_top_out[2]
 set_disable_timing sb_1__0_/chany_top_in[2]
 set_disable_timing sb_1__0_/chany_top_out[3]
 set_disable_timing sb_1__0_/chany_top_in[3]
+set_disable_timing sb_1__0_/chany_top_out[4]
 set_disable_timing sb_1__0_/chany_top_in[4]
 set_disable_timing sb_1__0_/chany_top_out[5]
 set_disable_timing sb_1__0_/chany_top_in[5]
@@ -958,9 +985,11 @@ set_disable_timing sb_1__0_/chanx_left_in[7]
 set_disable_timing sb_1__0_/chanx_left_out[7]
 set_disable_timing sb_1__0_/chanx_left_in[8]
 set_disable_timing sb_1__0_/chanx_left_out[8]
+set_disable_timing sb_1__0_/chanx_left_in[9]
 set_disable_timing sb_1__0_/chanx_left_out[9]
 set_disable_timing sb_1__0_/chanx_left_in[10]
 set_disable_timing sb_1__0_/chanx_left_out[10]
+set_disable_timing sb_1__0_/chanx_left_in[11]
 set_disable_timing sb_1__0_/chanx_left_out[11]
 set_disable_timing sb_1__0_/chanx_left_in[12]
 set_disable_timing sb_1__0_/chanx_left_out[12]
@@ -1050,7 +1079,9 @@ set_disable_timing sb_1__0_/mux_top_track_16/in[2]
 set_disable_timing sb_1__0_/mux_top_track_14/in[3]
 set_disable_timing sb_1__0_/mux_top_track_12/in[2]
 set_disable_timing sb_1__0_/mux_top_track_10/in[2]
+set_disable_timing sb_1__0_/mux_top_track_8/in[2]
 set_disable_timing sb_1__0_/mux_top_track_6/in[2]
+set_disable_timing sb_1__0_/mux_top_track_4/in[2]
 set_disable_timing sb_1__0_/mux_top_track_2/in[3]
 ##################################################
 # Disable timing for Switch block sb_1__1_
@@ -1058,9 +1089,11 @@ set_disable_timing sb_1__0_/mux_top_track_2/in[3]
 set_disable_timing sb_1__1_/chany_bottom_out[0]
 set_disable_timing sb_1__1_/chany_bottom_in[1]
 set_disable_timing sb_1__1_/chany_bottom_out[1]
+set_disable_timing sb_1__1_/chany_bottom_in[2]
 set_disable_timing sb_1__1_/chany_bottom_out[2]
 set_disable_timing sb_1__1_/chany_bottom_in[3]
 set_disable_timing sb_1__1_/chany_bottom_out[3]
+set_disable_timing sb_1__1_/chany_bottom_in[4]
 set_disable_timing sb_1__1_/chany_bottom_out[4]
 set_disable_timing sb_1__1_/chany_bottom_in[5]
 set_disable_timing sb_1__1_/chany_bottom_out[5]
@@ -1082,6 +1115,7 @@ set_disable_timing sb_1__1_/chanx_left_in[1]
 set_disable_timing sb_1__1_/chanx_left_in[2]
 set_disable_timing sb_1__1_/chanx_left_out[2]
 set_disable_timing sb_1__1_/chanx_left_in[3]
+set_disable_timing sb_1__1_/chanx_left_out[3]
 set_disable_timing sb_1__1_/chanx_left_in[4]
 set_disable_timing sb_1__1_/chanx_left_out[4]
 set_disable_timing sb_1__1_/chanx_left_in[5]
@@ -1166,6 +1200,7 @@ set_disable_timing sb_1__1_/mux_left_track_13/in[3]
 set_disable_timing sb_1__1_/mux_left_track_15/in[2]
 set_disable_timing sb_1__1_/mux_left_track_17/in[2]
 set_disable_timing sb_1__1_/mux_left_track_5/in[0]
+set_disable_timing sb_1__1_/mux_left_track_7/in[0]
 set_disable_timing sb_1__1_/mux_left_track_9/in[0]
 set_disable_timing sb_1__1_/mux_left_track_11/in[0]
 set_disable_timing sb_1__1_/mux_left_track_13/in[0]
@@ -1431,16 +1466,20 @@ set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/*
 #######################################
 set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/*
 #######################################
-# Disable Timing for unused grid[1][2][1]
+# Disable Timing for unused resources in grid[1][2][1]
 #######################################
 #######################################
-# Disable all the ports for pb_graph_node io[0]
+# Disable unused pins for pb_graph_node io[0]
 #######################################
-set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/*
+set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/io_inpad[0]
 #######################################
-# Disable all the ports for pb_graph_node iopad[0]
+# Disable unused mux_inputs for pb_graph_node io[0]
 #######################################
-set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
+set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1//direct_interc_0_/in[0]
+#######################################
+# Disable unused pins for pb_graph_node iopad[0]
+#######################################
+set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
 #######################################
 # Disable Timing for unused grid[1][2][2]
 #######################################
@@ -1559,20 +1598,16 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3//direct_interc
 #######################################
 set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
 #######################################
-# Disable Timing for unused resources in grid[2][1][4]
+# Disable Timing for unused grid[2][1][4]
 #######################################
 #######################################
-# Disable unused pins for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node io[0]
 #######################################
-set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/io_inpad[0]
+set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/*
 #######################################
-# Disable unused mux_inputs for pb_graph_node io[0]
+# Disable all the ports for pb_graph_node iopad[0]
 #######################################
-set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4//direct_interc_0_/in[0]
+set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/*
-#######################################
-# Disable unused pins for pb_graph_node iopad[0]
-#######################################
-set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
 #######################################
 # Disable Timing for unused grid[2][1][5]
 #######################################

openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_top_formal_verification.v

@@ -45,12 +45,11 @@ wire [0:0] clk_fm;
 // ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[14] -----
 	assign gfpga_pad_GPIO_PAD_fm[14] = b[0];
 
-// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
+// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[1] -----
-	assign c[0] = gfpga_pad_GPIO_PAD_fm[12];
+	assign c[0] = gfpga_pad_GPIO_PAD_fm[1];
 
 // ----- Wire unused FPGA I/Os to constants -----
 	assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
-	assign gfpga_pad_GPIO_PAD_fm[1] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[2] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[3] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[4] = 1'b0;
@@ -60,6 +59,7 @@ wire [0:0] clk_fm;
 	assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
+	assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
 	assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0;
@@ -132,8 +132,8 @@ initial begin
 	force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1000;
 	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
 	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
-	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
+	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
-	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
+	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
 	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
 	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
 	force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
@@ -154,8 +154,8 @@ initial begin
 	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
 	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
 	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
-	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
+	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
-	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
+	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
 	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
 	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
 	force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
@@ -238,12 +238,12 @@ initial begin
 	force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}};
@@ -288,12 +288,12 @@ initial begin
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}};
-	force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}};
@@ -302,12 +302,12 @@ initial begin
 	force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}};
-	force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10;
+	force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01;
+	force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = 2'b10;
+	force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = 2'b01;
+	force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}};
@@ -382,8 +382,8 @@ initial begin
 	force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
-	force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b1}};
+	force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
-	force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b0}};
+	force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
 	force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
 	force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
@@ -426,8 +426,8 @@ initial begin
 	force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
-	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
+	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = 3'b001;
-	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
+	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = 3'b110;
 	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}};
@@ -474,8 +474,8 @@ initial begin
 	force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}};
-	force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = 3'b101;
+	force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}};
-	force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = 3'b010;
+	force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}};
 	force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}};
 	force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}};

openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit

@@ -155,31 +155,6 @@
 0
 0
 0
-1
-0
-1
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
 0
 0
 0
@@ -223,7 +198,32 @@
 0
 0
 1
-1
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
 0
 0
 1
@@ -301,12 +301,12 @@
 0
 0
 0
-1
-1
 0
 0
-1
+0
-1
+0
+0
+0
 0
 0
 0
@@ -360,11 +360,6 @@
 1
 1
 1
-1
-1
-1
-1
-1
 0
 1
 1
@@ -378,6 +373,11 @@
 1
 1
 1
+1
+1
+1
+1
+1
 0
 0
 0
@@ -459,11 +459,11 @@
 0
 0
 0
-1
 0
 0
 0
-1
+0
+0
 0
 0
 0
@@ -472,12 +472,12 @@
 1
 0
 0
-1
+0
-1
+0
-0
+0
-0
+0
-1
+0
-1
+0
 0
 0
 0

openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml

@@ -314,11 +314,11 @@
 		</bit>
 		<bit id="373" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_5.mem_out[0]">
 		</bit>
-		<bit id="372" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[2]">
+		<bit id="372" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[2]">
 		</bit>
 		<bit id="371" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[1]">
 		</bit>
-		<bit id="370" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[0]">
+		<bit id="370" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[0]">
 		</bit>
 		<bit id="369" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[2]">
 		</bit>
@@ -398,7 +398,7 @@
 		</bit>
 		<bit id="331" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_2.mem_out[0]">
 		</bit>
-		<bit id="330" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_1.mem_out[2]">
+		<bit id="330" value="1" path="fpga_top.cbx_1__1_.mem_bottom_ipin_1.mem_out[2]">
 		</bit>
 		<bit id="329" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_1.mem_out[1]">
 		</bit>
@@ -448,9 +448,9 @@
 		</bit>
 		<bit id="306" value="0" path="fpga_top.sb_1__1_.mem_left_track_9.mem_out[0]">
 		</bit>
-		<bit id="305" value="1" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[1]">
+		<bit id="305" value="0" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[1]">
 		</bit>
-		<bit id="304" value="1" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[0]">
+		<bit id="304" value="0" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[0]">
 		</bit>
 		<bit id="303" value="0" path="fpga_top.sb_1__1_.mem_left_track_5.mem_out[1]">
 		</bit>
@@ -606,17 +606,17 @@
 		</bit>
 		<bit id="227" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_23.mem_out[0]">
 		</bit>
-		<bit id="226" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[1]">
+		<bit id="226" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[1]">
 		</bit>
-		<bit id="225" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[0]">
+		<bit id="225" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[0]">
 		</bit>
 		<bit id="224" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_19.mem_out[1]">
 		</bit>
 		<bit id="223" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_19.mem_out[0]">
 		</bit>
-		<bit id="222" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[1]">
+		<bit id="222" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[1]">
 		</bit>
-		<bit id="221" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[0]">
+		<bit id="221" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[0]">
 		</bit>
 		<bit id="220" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_15.mem_out[2]">
 		</bit>
@@ -724,7 +724,7 @@
 		</bit>
 		<bit id="168" value="1" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
 		</bit>
-		<bit id="167" value="1" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
+		<bit id="167" value="0" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
 		</bit>
 		<bit id="166" value="1" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
 		</bit>
@@ -734,7 +734,7 @@
 		</bit>
 		<bit id="163" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
 		</bit>
-		<bit id="162" value="0" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
+		<bit id="162" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
 		</bit>
 		<bit id="161" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
 		</bit>
@@ -922,7 +922,7 @@
 		</bit>
 		<bit id="69" value="0" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[1]">
 		</bit>
-		<bit id="68" value="1" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[0]">
+		<bit id="68" value="0" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[0]">
 		</bit>
 		<bit id="67" value="0" path="fpga_top.sb_1__0_.mem_top_track_6.mem_out[1]">
 		</bit>
@@ -930,7 +930,7 @@
 		</bit>
 		<bit id="65" value="0" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[1]">
 		</bit>
-		<bit id="64" value="1" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[0]">
+		<bit id="64" value="0" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[0]">
 		</bit>
 		<bit id="63" value="0" path="fpga_top.sb_1__0_.mem_top_track_2.mem_out[2]">
 		</bit>
@@ -948,17 +948,17 @@
 		</bit>
 		<bit id="56" value="0" path="fpga_top.sb_0__0_.mem_right_track_24.mem_out[0]">
 		</bit>
-		<bit id="55" value="1" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[1]">
+		<bit id="55" value="0" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[1]">
 		</bit>
-		<bit id="54" value="1" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[0]">
+		<bit id="54" value="0" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[0]">
 		</bit>
 		<bit id="53" value="0" path="fpga_top.sb_0__0_.mem_right_track_20.mem_out[1]">
 		</bit>
 		<bit id="52" value="0" path="fpga_top.sb_0__0_.mem_right_track_20.mem_out[0]">
 		</bit>
-		<bit id="51" value="1" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[1]">
+		<bit id="51" value="0" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[1]">
 		</bit>
-		<bit id="50" value="1" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[0]">
+		<bit id="50" value="0" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[0]">
 		</bit>
 		<bit id="49" value="0" path="fpga_top.sb_0__0_.mem_right_track_16.mem_out[1]">
 		</bit>

openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml

@@ -553,7 +553,7 @@
 						<instance level="4" name="GPIO_DFF_mem"/>
 					</hierarchy>
 					<bitstream>
-						<bit memory_port="mem_out[0]" value="1"/>
+						<bit memory_port="mem_out[0]" value="0"/>
 					</bitstream>
 				</bitstream_block>
 			</bitstream_block>
@@ -731,7 +731,7 @@
 						<instance level="4" name="GPIO_DFF_mem"/>
 					</hierarchy>
 					<bitstream>
-						<bit memory_port="mem_out[0]" value="0"/>
+						<bit memory_port="mem_out[0]" value="1"/>
 					</bitstream>
 				</bitstream_block>
 			</bitstream_block>
@@ -1480,15 +1480,15 @@
 				<instance level="2" name="mem_right_track_18"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_right_track_20" hierarchy_level="2">
@@ -1516,15 +1516,15 @@
 				<instance level="2" name="mem_right_track_22"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_right_track_24" hierarchy_level="2">
@@ -1961,16 +1961,16 @@
 				<instance level="2" name="mem_bottom_track_17"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_bottom_track_19" hierarchy_level="2">
@@ -2002,11 +2002,11 @@
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_bottom_track_23" hierarchy_level="2">
@@ -2098,13 +2098,13 @@
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="c"/>
+				<path id="2" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="2">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
 				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
@@ -2136,13 +2136,13 @@
 			<input_nets>
 				<path id="0" net_name="a"/>
 				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="c"/>
+				<path id="2" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="2">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
 				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
@@ -2864,16 +2864,16 @@
 				<instance level="2" name="mem_left_track_7"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_left_track_9" hierarchy_level="2">
@@ -2902,7 +2902,7 @@
 				<instance level="2" name="mem_left_track_11"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 			</input_nets>
@@ -3128,7 +3128,7 @@
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="c"/>
+				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -3174,7 +3174,7 @@
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="c"/>
+				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -3266,7 +3266,7 @@
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="c"/>
+				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -3287,7 +3287,7 @@
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="c"/>
+				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
@@ -3341,12 +3341,12 @@
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="c"/>
 			</output_nets>
-			<bitstream path_id="-1">
+			<bitstream path_id="3">
 				<bit memory_port="mem_out[0]" value="0"/>
 				<bit memory_port="mem_out[1]" value="0"/>
-				<bit memory_port="mem_out[2]" value="0"/>
+				<bit memory_port="mem_out[2]" value="1"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_bottom_ipin_2" hierarchy_level="2">
@@ -3382,7 +3382,7 @@
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="c"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
@@ -3403,7 +3403,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="c"/>
+				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
@@ -3541,7 +3541,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="c"/>
+				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
@@ -3616,7 +3616,7 @@
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="c"/>
+				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
 				<path id="0" net_name="unmapped"/>
@@ -3662,7 +3662,7 @@
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="c"/>
+				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
 				<path id="0" net_name="unmapped"/>
@@ -3754,7 +3754,7 @@
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="c"/>
+				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
 				<path id="0" net_name="unmapped"/>
@@ -3775,7 +3775,7 @@
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="c"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
@@ -3845,7 +3845,7 @@
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="c"/>
+				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
@@ -3866,7 +3866,7 @@
 				<instance level="2" name="mem_left_ipin_3"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
@@ -3891,18 +3891,18 @@
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="c"/>
+				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="a"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="2">
+			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[0]" value="0"/>
 				<bit memory_port="mem_out[1]" value="0"/>
-				<bit memory_port="mem_out[2]" value="1"/>
+				<bit memory_port="mem_out[2]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_left_ipin_5" hierarchy_level="2">
@@ -3912,7 +3912,7 @@
 				<instance level="2" name="mem_left_ipin_5"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
@@ -4004,7 +4004,7 @@
 				<instance level="2" name="mem_right_ipin_1"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>

openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/global_ports.sdc

@@ -14,7 +14,7 @@ set_units -time s
 ##################################################
 # Create clock                                    
 ##################################################
-create_clock -name clk[0] -period 1.618133072e-09 -waveform {0 8.09066536e-10} [get_ports {clk[0]}]
+create_clock -name clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10} [get_ports {clk[0]}]
 ##################################################
 # Create programmable clock                       
 ##################################################

openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/pin_mapping.xml

@@ -5,5 +5,5 @@
 <io_mapping>
 	<io name="gfpga_pad_GPIO_PAD[11:11]" net="a" dir="input"/>
 	<io name="gfpga_pad_GPIO_PAD[14:14]" net="b" dir="input"/>
-	<io name="gfpga_pad_GPIO_PAD[12:12]" net="c" dir="output"/>
+	<io name="gfpga_pad_GPIO_PAD[1:1]" net="c" dir="output"/>
 </io_mapping>

vtr-verilog-to-routing

@@ -1 +1 @@
-Subproject commit 04959b7b8aab26e6301fd554083bfe79bb5384ae
+Subproject commit 8178b71295d2579c38403529765c95432c44bd0c