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remove redudant net source addition in cbs and sbs

This commit is contained in:
tangxifan 2020-01-08 19:43:53 -07:00
parent f67981afa8
commit 2a3950470e
4 changed files with 69 additions and 4 deletions
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48
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp
View File

@ -326,6 +326,30 @@ vtr::vector<ModuleNetSrcId, size_t> ModuleManager::net_source_pins(const ModuleI
return net_src_pin_ids_[module][net];
}
/* Identify if a pin of a port in a module already exists in the net source list*/
bool ModuleManager::net_source_exist(const ModuleId& module, const ModuleNetId& net,
const ModuleId& src_module, const size_t& instance_id,
const ModulePortId& src_port, const size_t& src_pin) {
/* Validate module net */
VTR_ASSERT(valid_module_net_id(module, net));
/* Iterate over each source of the net.
* If a net source has the same src_module, instance_id, src_port and src_pin,
* we can say that the source has already been added to this net!
*/
for (const ModuleNetSrcId& net_src : module_net_sources(module, net)) {
if ( (src_module == net_source_modules(module, net)[net_src])
&& (instance_id == net_source_instances(module, net)[net_src])
&& (src_port == net_source_ports(module, net)[net_src])
&& (src_pin == net_source_pins(module, net)[net_src]) ) {
return true;
}
}
/* Reach here, it means nothing has been found. Return false */
return false;
}
/* Find the sink modules of a net */
vtr::vector<ModuleNetSinkId, ModuleId> ModuleManager::net_sink_modules(const ModuleId& module, const ModuleNetId& net) const {
/* Validate module net */
@ -358,6 +382,30 @@ vtr::vector<ModuleNetSinkId, size_t> ModuleManager::net_sink_pins(const ModuleId
return net_sink_pin_ids_[module][net];
}
/* Identify if a pin of a port in a module already exists in the net sink list*/
bool ModuleManager::net_sink_exist(const ModuleId& module, const ModuleNetId& net,
const ModuleId& sink_module, const size_t& instance_id,
const ModulePortId& sink_port, const size_t& sink_pin) {
/* Validate module net */
VTR_ASSERT(valid_module_net_id(module, net));
/* Iterate over each sink of the net.
* If a net sink has the same sink_module, instance_id, sink_port and sink_pin,
* we can say that the sink has already been added to this net!
*/
for (const ModuleNetSinkId& net_sink : module_net_sinks(module, net)) {
if ( (sink_module == net_sink_modules(module, net)[net_sink])
&& (instance_id == net_sink_instances(module, net)[net_sink])
&& (sink_port == net_sink_ports(module, net)[net_sink])
&& (sink_pin == net_sink_pins(module, net)[net_sink]) ) {
return true;
}
}
/* Reach here, it means nothing has been found. Return false */
return false;
}
/******************************************************************************
* Private Accessors
******************************************************************************/

9
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h
View File

@ -110,6 +110,10 @@ class ModuleManager {
vtr::vector<ModuleNetSrcId, ModulePortId> net_source_ports(const ModuleId& module, const ModuleNetId& net) const;
/* Find the source pin indices of a net */
vtr::vector<ModuleNetSrcId, size_t> net_source_pins(const ModuleId& module, const ModuleNetId& net) const;
/* Identify if a pin of a port in a module already exists in the net source list*/
bool net_source_exist(const ModuleId& module, const ModuleNetId& net,
const ModuleId& src_module, const size_t& instance_id,
const ModulePortId& src_port, const size_t& src_pin);
/* Find the sink modules of a net */
vtr::vector<ModuleNetSinkId, ModuleId> net_sink_modules(const ModuleId& module, const ModuleNetId& net) const;
@ -119,6 +123,11 @@ class ModuleManager {
vtr::vector<ModuleNetSinkId, ModulePortId> net_sink_ports(const ModuleId& module, const ModuleNetId& net) const;
/* Find the sink pin indices of a net */
vtr::vector<ModuleNetSinkId, size_t> net_sink_pins(const ModuleId& module, const ModuleNetId& net) const;
/* Identify if a pin of a port in a module already exists in the net sink list*/
bool net_sink_exist(const ModuleId& module, const ModuleNetId& net,
const ModuleId& sink_module, const size_t& instance_id,
const ModulePortId& sink_port, const size_t& sink_pin);
private: /* Private accessors */
size_t find_child_module_index_in_parent_module(const ModuleId& parent_module, const ModuleId& child_module) const;
public: /* Public mutators */

9
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp
View File

@ -149,8 +149,10 @@ void build_switch_block_mux_module(ModuleManager& module_manager,
for (size_t pin_id = 0; pin_id < sb_input_port_ids.size(); ++pin_id) {
/* Use the exising net */
ModuleNetId net = input_port_to_module_nets.at(sb_input_port_ids[pin_id]);
/* Configure the net source */
module_manager.add_module_net_source(sb_module, net, sb_module, 0, sb_input_port_ids[pin_id], 0);
/* Configure the net source only if it is not yet in the source list */
if (false == module_manager.net_source_exist(sb_module, net, sb_module, 0, sb_input_port_ids[pin_id], 0)) {
module_manager.add_module_net_source(sb_module, net, sb_module, 0, sb_input_port_ids[pin_id], 0);
}
/* Configure the net sink */
module_manager.add_module_net_sink(sb_module, net, mux_module, mux_instance_id, mux_input_port_id, mux_input_port.pins()[pin_id]);
}
@ -537,8 +539,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
for (size_t pin_id = 0; pin_id < cb_input_port_ids.size(); ++pin_id) {
/* Use the exising net */
ModuleNetId net = input_port_to_module_nets.at(cb_input_port_ids[pin_id]);
/* Configure the net source */
module_manager.add_module_net_source(cb_module, net, cb_module, 0, cb_input_port_ids[pin_id], 0);
/* No need to configure the net source since it is already done before */
/* Configure the net sink */
module_manager.add_module_net_sink(cb_module, net, mux_module, mux_instance_id, mux_input_port_id, mux_input_port.pins()[pin_id]);
}

7
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp
View File

@ -242,6 +242,7 @@ void print_verilog_module_local_short_connection(std::fstream& fp,
continue;
}
/* Find the source port and pin information */
print_verilog_comment(fp, std::string("----- Net source id " + std::to_string(size_t(net_src)) + " -----"));
ModulePortId src_port_id = module_manager.net_source_ports(module_id, module_net)[net_src];
size_t src_pin = module_manager.net_source_pins(module_id, module_net)[net_src];
BasicPort src_port(module_manager.module_port(module_id, src_port_id).get_name(), src_pin, src_pin);
@ -254,6 +255,7 @@ void print_verilog_module_local_short_connection(std::fstream& fp,
}
/* Find the sink port and pin information */
print_verilog_comment(fp, std::string("----- Net sink id " + std::to_string(size_t(net_sink)) + " -----"));
ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink];
size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink];
BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin);
@ -290,6 +292,7 @@ void print_verilog_module_local_short_connections(std::fstream& fp,
if (false == module_net_include_local_short_connection(module_manager, module_id, module_net)) {
continue;
}
print_verilog_comment(fp, std::string("----- Local connection due to Wire " + std::to_string(size_t(module_net)) + " -----"));
print_verilog_module_local_short_connection(fp, module_manager, module_id, module_net);
}
}
@ -455,10 +458,14 @@ void write_verilog_module_to_file(std::fstream& fp,
fp << std::endl;
/* Print local connection (from module inputs to output! */
print_verilog_comment(fp, std::string("----- BEGIN Local short connections -----"));
print_verilog_module_local_short_connections(fp, module_manager, module_id);
print_verilog_comment(fp, std::string("----- END Local short connections -----"));
print_verilog_comment(fp, std::string("----- BEGIN Local output short connections -----"));
print_verilog_module_output_short_connections(fp, module_manager, module_id);
print_verilog_comment(fp, std::string("----- END Local output short connections -----"));
/* Print an empty line as splitter */
fp << std::endl;