yosys techlib directory restructure

openfpga_flow/openfpga_timing_annotation/README.md

@@ -0,0 +1,27 @@
+Naming convention for timing annotation files
+Convention follows the VPR architecture file naming convention, with some extra detail appended to the end.
+
+k<lut_size>: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size.
+The keyword 'frac' is to specify if fracturable LUT is used or not.
+The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch).
+N<le_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
+tileable: If the routing architecture is tileable or not.
+The keyword 'IO' specifies if the I/O tile is tileable or not
+fracdff: Use multi-mode DFF model, where reset/set/clock polarity is configurable
+adder_chain: If hard adder/carry chain is used inside CLBs
+register_chain: If shift register chain is used inside CLBs
+scan_chain: If scan chain testing infrastructure is used inside CLBs
+__mem<mem_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword 'wide' is to specify if the BRAM spans more than 1 column. The keyword 'frac' is to specify if the BRAM is fracturable to operate in different modes.
+__dsp<dsp_size>: If Digital Signal Processor (DSP) is used or not. If used, the input size should be clarified here. The keyword 'wide' is to specify if the DSP spans more than 1 column. The keyword 'frac' is to specify if the DSP is fracturable to operate in different modes.
+aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
+multi_io_capacity: If I/O capacity is different on each side of FPGAs.
+reduced_io: If I/Os only appear a certain or multiple sides of FPGAs
+registerable_io: If I/Os are registerable (can be either combinational or sequential)
+<feature_size>: The technology node which the delay numbers are extracted from.
+TileOrgz: How tile is organized.
+Top-left (Tl): the pins of a tile are placed on the top side and left side only
+Top-right (Tr): the pins of a tile are placed on the top side and right side only
+Bottom-right (Br): the pins of a tile are placed on the bottom side and right side only
+GlobalTileClk: How many clocks are defined through global ports from physical tiles. is the number of clocks
+Other features are used in naming should be listed here.
+

openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml

@@ -1,33 +1,17 @@
-L1_SB_MUX_DELAY: 1.44e-9
-L2_SB_MUX_DELAY: 1.44e-9
-L4_SB_MUX_DELAY: 1.44e-9
-CB_MUX_DELAY: 1.38e-9
-L1_WIRE_R: 100
-L1_WIRE_C: 1e-12
-L2_WIRE_R: 100
-L2_WIRE_C: 1e-12
-L4_WIRE_R: 100
-L4_WIRE_C: 1e-12
 INPAD_DELAY: 0.11e-9
 OUTPAD_DELAY: 0.11e-9
 FF_T_SETUP: 0.39e-9
 FF_T_CLK2Q: 0.43e-9
-LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
-LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
 LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
 FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
 LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
 FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
-LUT3_DELAY: 0.92e-9
-LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
 LUT4_DELAY: 1.21e-9
 LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
 LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE
 LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
 LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE
 LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
-REGIN_TO_FF0_DELAY: 1.12e-9
-FF0_TO_FF1_DELAY: 0.56e-9
 
 CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE
 CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE
@@ -38,25 +22,16 @@ CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
 
 ################# Adder Delays #################
 
-ADDER_LUT4_CIN2OUT_DELAY: 1.21e-9
-ADDER_LUT4_CIN2COUT_DELAY: 1.21e-9
-ADDER_LUT4_IN2OUT_DELAY: 1.21e-9
-ADDER_LUT4_IN2COUT_DELAY: 1.21e-9
+ADDER_CIN2OUT_DELAY: 1.21e-9
+ADDER_CIN2COUT_DELAY: 1.21e-9
+ADDER_IN2OUT_DELAY: 1.21e-9
+ADDER_IN2COUT_DELAY: 1.21e-9
 
 ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
 ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
 
 
 
-################# MULT9 Delays #################
-
-MULT9_A2Y_DELAY_MAX: 1.523e-9
-MULT9_A2Y_DELAY_MIN: 0.776e-9
-MULT9_B2Y_DELAY_MAX: 1.523e-9
-MULT9_B2Y_DELAY_MIN: 0.776e-9
-
-
-
 ################# MULT18 Delays #################
 
 MULT18_A2Y_DELAY_MAX: 1.523e-9

openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml

@@ -0,0 +1,47 @@
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE
+LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE
+LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+
+CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE
+CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE
+
+CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
+
+
+
+################# Adder Delays #################
+
+ADDER_CIN2OUT_DELAY: 1.21e-9
+ADDER_CIN2COUT_DELAY: 1.21e-9
+ADDER_IN2OUT_DELAY: 1.21e-9
+ADDER_IN2COUT_DELAY: 1.21e-9
+
+ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
+ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
+
+
+
+################# BRAM Delays #################
+
+DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9
+
+MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
+MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12
+MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12
+MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12
+MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12
+BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12

openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm_tt.yml

@@ -0,0 +1,44 @@
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE
+LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE
+LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+
+CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE
+CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE
+
+CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
+
+
+
+################# Adder Delays #################
+
+ADDER_CIN2OUT_DELAY: 1.21e-9
+ADDER_CIN2COUT_DELAY: 1.21e-9
+ADDER_IN2OUT_DELAY: 1.21e-9
+ADDER_IN2COUT_DELAY: 1.21e-9
+
+ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
+ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
+
+
+
+################# MULT18 Delays #################
+
+MULT18_A2Y_DELAY_MAX: 1.523e-9
+MULT18_A2Y_DELAY_MIN: 0.776e-9
+MULT18_B2Y_DELAY_MAX: 1.523e-9
+MULT18_B2Y_DELAY_MIN: 0.776e-9
+MULT18_SLICE_A2A_DELAY_MAX: 134e-12 # MULT18_SLICE_A2A_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_A2A_DELAY_MIN: 74e-12 # MULT18_SLICE_A2A_DELAY_MIN NOT ACCURATE
+MULT18_SLICE_B2B_DELAY_MAX: 134e-12 # MULT18_SLICE_B2B_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_B2B_DELAY_MIN: 74e-12 # MULT18_SLICE_B2B_DELAY_MIN NOT ACCURATE
+MULT18_SLICE_OUT2OUT_DELAY_MAX: 1.93e-9 # MULT18_SLICE_OUT2OUT_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_OUT2OUT_DELAY_MIN: 74e-12 # MULT18_SLICE_OUT2OUT_DELAY_MIN NOT ACCURATE