From 29e80d157ccf85be07262d170adf88ccfe1282ec Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 13 Sep 2019 21:27:47 -0600
Subject: [PATCH] Start developing BitstreamContext

---
 .../vpr/SRC/fpga_x2p/base/bitstream_context.h | 31 +++++++++++++++++++
 .../SRC/fpga_x2p/base/bitstream_context_fwd.h | 18 +++++++++++
 2 files changed, 49 insertions(+)
 create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h
 create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h

diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h
new file mode 100644
index 000000000..6ee011182
--- /dev/null
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h
@@ -0,0 +1,31 @@
+/******************************************************************************
+ * This file introduces a data structure to store bitstream-related information 
+ ******************************************************************************/
+#ifndef BITSTREAM_CONTEXT_H
+#define BITSTREAM_CONTEXT_H
+
+#include "vtr_vector.h"
+#include "bitstream_context_fwd.h"
+
+class BitstreamContext {
+  private: /* Internal data */
+    enum e_sram_orgz config_scheme_;  /* The type of configuration protocol */
+    CircuitModelId& sram_model_;      /* The memory circuit model used by the Bitstream generation */
+    size_t num_memory_bits_;          /* Number of memory bits */ 
+    size_t num_bls_;                  /* Number of Bit Lines */
+    size_t num_wls_;                  /* Number of Word Lines */
+
+    size_t num_reserved_bls_;         /* Number of reserved Bit Lines, ONLY applicable to RRAM-based FPGA */
+    size_t num_reserved_wls_;         /* Number of reserved Word Lines, ONLY applicable to RRAM-based FPGA  */
+    /* Unique id of a bit in the Bitstream */
+    vtr::vector<ConfigBitId, ConfigBitId> bit_ids_; 
+    /* Bit line address of a bit in the Bitream: ONLY applicable to memory-decoders */
+    vtr::vector<ConfigBitId, size_t> bl_addr_;     
+    /* Word line address of a bit in the Bitream: ONLY applicable to memory-decoders */
+    vtr::vector<ConfigBitId, size_t> wl_addr_;     
+    /* value of a bit in the Bitream */
+    vtr::vector<ConfigBitId, bool> bit_val_;
+};
+
+#endif
+
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h
new file mode 100644
index 000000000..29d85580e
--- /dev/null
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h
@@ -0,0 +1,18 @@
+/**************************************************
+ * This file includes only declarations for 
+ * the data structures for module managers
+ * Please refer to module_manager.h for more details
+ *************************************************/
+#ifndef MODULE_MANAGER_FWD_H
+#define MODULE_MANAGER_FWD_H
+
+#include "vtr_strong_id.h"
+
+/* Strong Ids for ModuleManager */
+struct config_bit_id_tag;
+
+typedef vtr::StrongId<config_bit_id_tag> ConfigBitId;
+
+class BitstreamContext;
+
+#endif