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[core] fixed syntax errors

This commit is contained in:
tangxifan 2023-04-22 15:09:39 +08:00
parent 5e8e982334
commit 297a23dee7
6 changed files with 30 additions and 27 deletions
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39
libs/libarchopenfpga/src/config_protocol.cpp
View File

@ -1,3 +1,4 @@
#include "openfpga_tokenizer.h"
#include "config_protocol.h" #include "config_protocol.h"
#include "vtr_assert.h" #include "vtr_assert.h"
@ -27,32 +28,32 @@ CircuitModelId ConfigProtocol::memory_model() const { return memory_model_; }
int ConfigProtocol::num_regions() const { return num_regions_; } int ConfigProtocol::num_regions() const { return num_regions_; }
std::vector<BasicPort> ConfigProtocol::prog_clock_ports() const { std::vector<openfpga::BasicPort> ConfigProtocol::prog_clock_ports() const {
std::vector<BasicPort> keys; std::vector<openfpga::BasicPort> keys;
for (const auto& [k, v] : prog_clk_ccff_head_indices_) { for (const auto& [k, v] : prog_clk_ccff_head_indices_) {
keys.push_back(k); keys.push_back(k);
} }
return keys; return keys;
} }
std::string ConfigProtocol::prog_clock_port_ccff_head_indices(const BasicPort& port) const { std::string ConfigProtocol::prog_clock_port_ccff_head_indices_str(const openfpga::BasicPort& port) const {
std::string ret(""); std::string ret("");
std::vector<size_t> raw = prog_clock_port_ccff_head_indices(port); std::vector<size_t> raw = prog_clock_port_ccff_head_indices(port);
if (!raw.empty()) { if (!raw.empty()) {
for (size_t idx : raw) { for (size_t idx : raw) {
/* TODO: We need a join function */ /* TODO: We need a join function */
ret += std::to_string(idx) + std::string(INDICE_STRING_DELIM); ret += std::to_string(idx) + std::to_string(INDICE_STRING_DELIM_);
} }
/* Remove the last comma */ /* Remove the last comma */
ret.pop(); ret.pop_back();
} }
return ret; return ret;
} }
std::vector<size_t> ConfigProtocol::prog_clock_port_ccff_head_indices(const BasicPort& port) const { std::vector<size_t> ConfigProtocol::prog_clock_port_ccff_head_indices(const openfpga::BasicPort& port) const {
std::vector<size_t> ret; std::vector<size_t> ret;
auto result = prog_clk_ccff_head_indices.find(port); auto result = prog_clk_ccff_head_indices_.find(port);
if (result != prog_clk_ccff_head_indices.end()) { if (result != prog_clk_ccff_head_indices_.end()) {
return result->second; return result->second;
} }
return ret; return ret;
@ -106,16 +107,16 @@ void ConfigProtocol::set_num_regions(const int& num_regions) {
num_regions_ = num_regions; num_regions_ = num_regions;
} }
void ConfigProtocol::set_prog_clock_port_ccff_head_indices_pair(const BasicPort& port, const std::string& indices_str) { void ConfigProtocol::set_prog_clock_port_ccff_head_indices_pair(const openfpga::BasicPort& port, const std::string& indices_str) {
openfpga::StringToken tokenizer(indices_str); openfpga::StringToken tokenizer(indices_str);
std::vector<int> token_int; std::vector<size_t> token_int;
token_int.reserve(tokenizer.split(INDICE_STRING_DELIM_).size()); token_int.reserve(tokenizer.split(INDICE_STRING_DELIM_).size());
for (std::string token : tokenizer.split(INDICE_STRING_DELIM_)) { for (std::string token : tokenizer.split(INDICE_STRING_DELIM_)) {
token_int.push_back(std::atoi(token)); token_int.push_back(std::stoi(token));
} }
auto result = prog_clk_ccff_head_indices.find(port); auto result = prog_clk_ccff_head_indices_.find(port);
if (result != prog_clk_ccff_head_indices.end()) { if (result != prog_clk_ccff_head_indices_.end()) {
VTR_LOG_WARN("Overwrite the pair between programming clock port '%s[%d:%d]' and ccff head indices (previous: '%s', current: '%s')!\n", port.get_name().c_str(), port.get_lsb(), port.get_msb(), prog_clock_port_ccff_head_indices(port).c_str(), indices_str.c_str()); VTR_LOG_WARN("Overwrite the pair between programming clock port '%s[%d:%d]' and ccff head indices (previous: '%s', current: '%s')!\n", port.get_name().c_str(), port.get_lsb(), port.get_msb(), prog_clock_port_ccff_head_indices_str(port).c_str(), indices_str.c_str());
} }
prog_clk_ccff_head_indices_[port] = token_int; prog_clk_ccff_head_indices_[port] = token_int;
} }
@ -205,11 +206,11 @@ void ConfigProtocol::set_wl_num_banks(const size_t& num_banks) {
/************************************************************************ /************************************************************************
* Private Validators * Private Validators
***********************************************************************/ ***********************************************************************/
int ConfigProtocol::validate_ccff_prog_clocks() { int ConfigProtocol::validate_ccff_prog_clocks() const {
int num_err = 0; int num_err = 0;
/* Initialize scoreboard */ /* Initialize scoreboard */
std::vector<int> ccff_head_scoreboard(num_regions(), 0); std::vector<int> ccff_head_scoreboard(num_regions(), 0);
for (BasicPort port : prog_clock_ports()) { for (openfpga::BasicPort port : prog_clock_ports()) {
/* Must be valid first */ /* Must be valid first */
if (port.is_valid()) { if (port.is_valid()) {
VTR_LOG_ERROR("Programming clock '%s[%d:%d]' is not a valid port!\n", port.get_name().c_str(), port.get_lsb(), port.get_msb()); VTR_LOG_ERROR("Programming clock '%s[%d:%d]' is not a valid port!\n", port.get_name().c_str(), port.get_lsb(), port.get_msb());
@ -222,14 +223,14 @@ int ConfigProtocol::validate_ccff_prog_clocks() {
} }
/* Fill scoreboard */ /* Fill scoreboard */
for (size_t ccff_head_idx : prog_clock_port_ccff_head_indices(port)) { for (size_t ccff_head_idx : prog_clock_port_ccff_head_indices(port)) {
if (ccff_head_idx => ccff_head_scoreboard.size()) { if (ccff_head_idx >= ccff_head_scoreboard.size()) {
VTR_LOG_ERROR("Programming clock '%s[%d:%d]' controlls an invalid ccff head '%ld' (Expect [0, '%ld'])!\n", port.get_name().c_str(), port.get_lsb(), port.get_msb(), ccff_head_idx, ccff_head_scoreboard.size() - 1); VTR_LOG_ERROR("Programming clock '%s[%d:%d]' controlls an invalid ccff head '%ld' (Expect [0, '%ld'])!\n", port.get_name().c_str(), port.get_lsb(), port.get_msb(), ccff_head_idx, ccff_head_scoreboard.size() - 1);
num_err++; num_err++;
} }
ccff_head_scoreboard[ccff_head_idx]++; ccff_head_scoreboard[ccff_head_idx]++;
} }
} }
if (prog_clock_ports().size() != num_regions()) { if (prog_clock_ports().size() != (size_t)num_regions()) {
VTR_LOG_ERROR("Number of programming clocks '%ld' does not match the number of configuration regions '%ld'!\n", prog_clock_ports().size(), num_regions()); VTR_LOG_ERROR("Number of programming clocks '%ld' does not match the number of configuration regions '%ld'!\n", prog_clock_ports().size(), num_regions());
num_err++; num_err++;
} }
@ -249,7 +250,7 @@ int ConfigProtocol::validate_ccff_prog_clocks() {
/************************************************************************ /************************************************************************
* Public Validators * Public Validators
***********************************************************************/ ***********************************************************************/
int ConfigProtocol::validate() { int ConfigProtocol::validate() const {
int num_err = 0; int num_err = 0;
if (type() == CONFIG_MEM_SCAN_CHAIN) { if (type() == CONFIG_MEM_SCAN_CHAIN) {
num_err += validate_ccff_prog_clocks(); num_err += validate_ccff_prog_clocks();

11
libs/libarchopenfpga/src/config_protocol.h
View File

@ -2,6 +2,7 @@
#define CONFIG_PROTOCOL_H #define CONFIG_PROTOCOL_H
#include <string> #include <string>
#include <map>
#include "circuit_library_fwd.h" #include "circuit_library_fwd.h"
#include "circuit_types.h" #include "circuit_types.h"
@ -31,10 +32,10 @@ class ConfigProtocol {
int num_regions() const; int num_regions() const;
/* Get a list of programming clock ports */ /* Get a list of programming clock ports */
std::vector<BasicPort> prog_clock_ports() const; std::vector<openfpga::BasicPort> prog_clock_ports() const;
/* Get a list of programming clock ports */ /* Get a list of programming clock ports */
std::string prog_clock_port_ccff_head_indices(const BasicPort& port) const; std::string prog_clock_port_ccff_head_indices_str(const openfpga::BasicPort& port) const;
std::vector<size_t> prog_clock_port_ccff_head_indices(const BasicPort& port) const; std::vector<size_t> prog_clock_port_ccff_head_indices(const openfpga::BasicPort& port) const;
e_blwl_protocol_type bl_protocol_type() const; e_blwl_protocol_type bl_protocol_type() const;
std::string bl_memory_model_name() const; std::string bl_memory_model_name() const;
@ -51,7 +52,7 @@ class ConfigProtocol {
void set_num_regions(const int& num_regions); void set_num_regions(const int& num_regions);
/* Add a pair of programming clock port and ccff head indices. This API will parse the index list, e.g., "0,1" to a vector of integers [0 1] */ /* Add a pair of programming clock port and ccff head indices. This API will parse the index list, e.g., "0,1" to a vector of integers [0 1] */
void set_prog_clock_port_ccff_head_indices_pair(const BasicPort& port, const std::string& indices_str); void set_prog_clock_port_ccff_head_indices_pair(const openfpga::BasicPort& port, const std::string& indices_str);
void set_bl_protocol_type(const e_blwl_protocol_type& type); void set_bl_protocol_type(const e_blwl_protocol_type& type);
void set_bl_memory_model_name(const std::string& memory_model_name); void set_bl_memory_model_name(const std::string& memory_model_name);
@ -90,7 +91,7 @@ class ConfigProtocol {
int num_regions_; int num_regions_;
/* Programming clock managment: This is only applicable to configuration chain protocols */ /* Programming clock managment: This is only applicable to configuration chain protocols */
std::map<BasicPort, std::vector<size_t>> prog_clk_ccff_head_indices_; std::map<openfpga::BasicPort, std::vector<size_t>> prog_clk_ccff_head_indices_;
char INDICE_STRING_DELIM_; char INDICE_STRING_DELIM_;
/* BL & WL protocol: This is only applicable to memory-bank configuration /* BL & WL protocol: This is only applicable to memory-bank configuration

2
libs/libarchopenfpga/src/read_xml_config_protocol.cpp
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@ -60,7 +60,7 @@ static void read_xml_ccff_prog_clock(pugi::xml_node& xml_progclk,
std::string indices_attr = std::string indices_attr =
get_attribute(xml_progclk, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR, loc_data).as_string(); get_attribute(xml_progclk, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR, loc_data).as_string();
BasicPort port = openfpga::PortParser(port_attr).port(); openfpga::BasicPort port = openfpga::PortParser(port_attr).port();
config_protocol.set_prog_clock_port_ccff_head_indices_pair(port, indices_attr); config_protocol.set_prog_clock_port_ccff_head_indices_pair(port, indices_attr);
} }

2
libs/libarchopenfpga/src/write_xml_config_protocol.cpp
View File

@ -48,7 +48,7 @@ static void write_xml_config_organization(std::fstream& fp, const char* fname,
port.to_verilog_string().c_str()); port.to_verilog_string().c_str());
write_xml_attribute( write_xml_attribute(
fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR, fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR,
config_protocol.prog_clock_port_ccff_head_indices(port).c_str()); config_protocol.prog_clock_port_ccff_head_indices_str(port).c_str());
fp << "/>" fp << "/>"
<< "\n"; << "\n";
} }

1
openfpga/src/base/openfpga_read_arch_template.h
View File

@ -4,6 +4,7 @@
* This file includes functions to read an OpenFPGA architecture file * This file includes functions to read an OpenFPGA architecture file
* which are built on the libarchopenfpga library * which are built on the libarchopenfpga library
*******************************************************************/ *******************************************************************/
#include "check_config_protocol.h"
#include "check_circuit_library.h" #include "check_circuit_library.h"
#include "check_tile_annotation.h" #include "check_tile_annotation.h"
#include "circuit_library_utils.h" #include "circuit_library_utils.h"

2
openfpga/src/utils/check_config_protocol.cpp
View File

@ -16,7 +16,7 @@ namespace openfpga {
/******************************************************************** /********************************************************************
* Check if the programming clock port defined in configuration protocol is a valid global programming clock of a ccff model * Check if the programming clock port defined in configuration protocol is a valid global programming clock of a ccff model
*******************************************************************/ *******************************************************************/
int check_config_protocol_programming_clock( static int check_config_protocol_programming_clock(
const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib) { const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib) {
int num_err = 0; int num_err = 0;
/* Programming clock is only available for CCFF */ /* Programming clock is only available for CCFF */