From 297092f1fe93a752ae773c88d39cd78aafecb802 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 14 Jan 2023 22:12:00 -0800
Subject: [PATCH] [arch] now use a local clock as an input of a CLB

---
 ...4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml |  4 ++--
 .../k4_frac_N4_tileable_fracff_localClkGen_40nm.xml  | 12 ++++++++----
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml
index df8f9b37c..7a7154031 100644
--- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml
@@ -200,8 +200,8 @@
     <segment name="L4" circuit_model_name="chan_segment"/>
   </routing_segment>
   <tile_annotations>
-    <global_port name="op_clk" tile_port="clb.clk[1]" is_clock="true" default_val="0">
-      <tile name="clb" port="clk[1]"/>
+    <global_port name="op_clk" tile_port="clb.clk" is_clock="true" default_val="0">
+      <tile name="clb" port="clk"/>
     </global_port>
     <global_port name="op_reset" is_reset="true" default_val="0">
       <tile name="clb" port="reset"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
index 9d4d8d737..1b127942d 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
@@ -102,9 +102,11 @@
         <input name="I" num_pins="12" equivalent="full"/>
         <input name="reset" num_pins="1" is_non_clock_global="true"/>
         <output name="O" num_pins="8" equivalent="none"/>
-        <clock name="clk" num_pins="2" equivalent="full"/>
+        <!-- Local clock -->
+        <input name="lclk" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
         <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-          <fc_override port_name="clk[1]" fc_type="frac" fc_val="0"/>
+          <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
           <fc_override port_name="reset" fc_type="frac" fc_val="0"/>
         </fc>
         <pinlocations pattern="spread"/>
@@ -276,7 +278,9 @@
       <input name="I" num_pins="12" equivalent="full"/>
       <input name="reset" num_pins="1"/>
       <output name="O" num_pins="8" equivalent="none"/>
-      <clock name="clk" num_pins="2" equivalent="full"/>
+      <!-- Local clock -->
+      <input name="lclk" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
       <!-- Describe fracturable logic element.  
              Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
              The outputs of the fracturable logic element can be optionally registered
@@ -611,7 +615,7 @@
           <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
           <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
         </complete>
-        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+        <complete name="clks" input="clb.lclk clb.clk" output="fle[3:0].clk">
         </complete>
         <complete name="resets" input="clb.reset" output="fle[3:0].reset">
         </complete>