From 286df309471a73934e1b6b778f5a33fe1a20c218 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 29 Jun 2024 11:02:17 -0700
Subject: [PATCH] [test] update clock arch xml syntax

---
 .../config/clk_arch_1clk_1rst_2layer.xml                  | 8 ++++----
 .../config/clk_arch_1clk_1rst_2layer.xml                  | 8 ++++----
 .../config/clk_arch_1clk_1rst_2layer_int_driver.xml       | 8 ++++----
 .../homo_1clock_2layer/config/clk_arch_1clk_2layer.xml    | 2 +-
 .../config/clk_arch_1clk_2layer.xml                       | 2 +-
 .../homo_2clock_2layer/config/clk_arch_2clk_2layer.xml    | 2 +-
 .../config/clk_arch_2clk_2layer.xml                       | 2 +-
 .../config/clk_arch_2clk_2layer.xml                       | 2 +-
 8 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml
index 6c05921c7..3f499fedf 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml
@@ -1,5 +1,5 @@
 <clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0"> 
-  <clock_network name="clk_tree_2lvl" width="1"> 
+  <clock_network name="clk_tree_2lvl" global_port="op_clk[0:0]"> 
     <spine name="clk_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
       <switch_point tap="clk_rib_lvl1_sw0_upper" x="1" y="1"/> 
       <switch_point tap="clk_rib_lvl1_sw0_lower" x="1" y="1"/> 
@@ -11,10 +11,10 @@
     <spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <all from_pin="rst[0:0]" to_pin="clb[0:0].clk[0:0]"/>
+      <all from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
     </taps>
   </clock_network>  
-  <clock_network name="rst_tree_2lvl" width="1"> 
+  <clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]"> 
     <spine name="rst_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
       <switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1"/> 
       <switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1"/> 
@@ -26,7 +26,7 @@
     <spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <all from_pin="rst[0:0]" to_pin="clb[0:0].reset[0:0]"/>
+      <all from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]"/>
     </taps>
   </clock_network>  
 </clock_networks> 
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml
index 6c05921c7..3f499fedf 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml
@@ -1,5 +1,5 @@
 <clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0"> 
-  <clock_network name="clk_tree_2lvl" width="1"> 
+  <clock_network name="clk_tree_2lvl" global_port="op_clk[0:0]"> 
     <spine name="clk_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
       <switch_point tap="clk_rib_lvl1_sw0_upper" x="1" y="1"/> 
       <switch_point tap="clk_rib_lvl1_sw0_lower" x="1" y="1"/> 
@@ -11,10 +11,10 @@
     <spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <all from_pin="rst[0:0]" to_pin="clb[0:0].clk[0:0]"/>
+      <all from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
     </taps>
   </clock_network>  
-  <clock_network name="rst_tree_2lvl" width="1"> 
+  <clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]"> 
     <spine name="rst_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
       <switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1"/> 
       <switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1"/> 
@@ -26,7 +26,7 @@
     <spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <all from_pin="rst[0:0]" to_pin="clb[0:0].reset[0:0]"/>
+      <all from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]"/>
     </taps>
   </clock_network>  
 </clock_networks> 
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml
index ed43a26b5..c88e8ccd4 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml
@@ -1,5 +1,5 @@
 <clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0"> 
-  <clock_network name="clk_tree_2lvl" width="1"> 
+  <clock_network name="clk_tree_2lvl" global_port="op_clk[0:0]"> 
     <spine name="clk_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
       <switch_point tap="clk_rib_lvl1_sw0_upper" x="1" y="1"> 
         <internal_driver tile_pin="clb.O[0:7]"/>
@@ -19,10 +19,10 @@
     <spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
+      <all from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
     </taps>
   </clock_network>  
-  <clock_network name="rst_tree_2lvl" width="1"> 
+  <clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]"> 
     <spine name="rst_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
       <switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1"/> 
       <switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1"/> 
@@ -34,7 +34,7 @@
     <spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <all from_pin="rst[0:0]" to_pin="clb[0:0].reset[0:0]"/>
+      <all from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]"/>
     </taps>
   </clock_network>  
 </clock_networks> 
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml
index 7a41f1216..6f289dbf4 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml
@@ -1,5 +1,5 @@
 <clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0"> 
-  <clock_network name="clk_tree_2lvl" width="1"> 
+  <clock_network name="clk_tree_2lvl" global_port="clk[0:0]"> 
     <spine name="spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
       <switch_point tap="rib_lvl1_sw0_upper" x="1" y="1"/> 
       <switch_point tap="rib_lvl1_sw0_lower" x="1" y="1"/> 
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml
index 7a41f1216..6f289dbf4 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml
@@ -1,5 +1,5 @@
 <clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0"> 
-  <clock_network name="clk_tree_2lvl" width="1"> 
+  <clock_network name="clk_tree_2lvl" global_port="clk[0:0]"> 
     <spine name="spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
       <switch_point tap="rib_lvl1_sw0_upper" x="1" y="1"/> 
       <switch_point tap="rib_lvl1_sw0_lower" x="1" y="1"/> 
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml
index 8c224318c..98e91d27a 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml
@@ -1,5 +1,5 @@
 <clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0"> 
-  <clock_network name="clk_tree_2lvl" width="2"> 
+  <clock_network name="clk_tree_2lvl" global_port="clk[0:1]"> 
     <spine name="spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
       <switch_point tap="rib_lvl1_sw0_upper" x="1" y="1"/> 
       <switch_point tap="rib_lvl1_sw0_lower" x="1" y="1"/> 
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml
index 8c224318c..98e91d27a 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml
@@ -1,5 +1,5 @@
 <clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0"> 
-  <clock_network name="clk_tree_2lvl" width="2"> 
+  <clock_network name="clk_tree_2lvl" global_port="clk[0:1]"> 
     <spine name="spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
       <switch_point tap="rib_lvl1_sw0_upper" x="1" y="1"/> 
       <switch_point tap="rib_lvl1_sw0_lower" x="1" y="1"/> 
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml
index 8c224318c..98e91d27a 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml
@@ -1,5 +1,5 @@
 <clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0"> 
-  <clock_network name="clk_tree_2lvl" width="2"> 
+  <clock_network name="clk_tree_2lvl" global_port="clk[0:1]"> 
     <spine name="spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
       <switch_point tap="rib_lvl1_sw0_upper" x="1" y="1"/> 
       <switch_point tap="rib_lvl1_sw0_lower" x="1" y="1"/>