[HDL] Add yosys technology library for reworked architecture using 16k-bit DPRAM

openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram.txt

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+bram $__MY_DPRAM_2048x8
+  init 0
+  abits 12
+  dbits 8
+  groups 2
+  ports  1  1
+  wrmode 1  0
+  enable 1  1
+  transp 0  0
+  clocks 1  1
+  clkpol 1  1
+endbram
+
+match $__MY_DPRAM_2048x8
+  min efficiency 0
+  make_transp
+endmatch
+

openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram_map.v

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+module $__MY_DPRAM_2048x8 (
+  output [0:7] B1DATA,
+  input CLK1,
+  input [0:11] B1ADDR,
+  input [0:11] A1ADDR,
+  input [0:7] A1DATA,
+  input A1EN,
+  input B1EN );
+
+  generate
+    dpram_2048x8 #() _TECHMAP_REPLACE_ (
+      .clk    (CLK1),
+      .wen    (A1EN),
+      .waddr    (A1ADDR),
+      .data_in    (A1DATA),
+      .ren    (B1EN),
+      .raddr    (B1ADDR),
+      .data_out    (B1DATA) );
+  endgenerate
+
+endmodule

openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_cell_sim.v

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+//-----------------------------
+// Dual-port RAM 2048x8 bit (8Kbit)
+// Core logic
+//-----------------------------
+module dpram_2048x8_core (
+  input wclk,
+  input wen,
+  input [0:11] waddr,
+  input [0:7] data_in,
+  input rclk,
+  input ren,
+  input [0:11] raddr,
+  output [0:7] data_out );
+
+  reg [0:7] ram[0:2047];
+  reg [0:7] internal;
+
+  assign data_out = internal;
+
+  always @(posedge wclk) begin
+    if(wen) begin
+      ram[waddr] <= data_in;
+    end
+  end
+
+  always @(posedge rclk) begin
+    if(ren) begin
+      internal <= ram[raddr];
+    end
+  end
+
+endmodule
+
+//-----------------------------
+// Dual-port RAM 2048x8 bit (8Kbit) wrapper
+// where the read clock and write clock
+// are combined to a unified clock
+//-----------------------------
+module dpram_2048x8 (
+  input clk,
+  input wen,
+  input ren,
+  input [0:11] waddr,
+  input [0:11] raddr,
+  input [0:7] data_in,
+  output [0:7] data_out );
+
+    dpram_2048x8_core memory_0 (
+      .wclk    (clk),
+      .wen    (wen),
+      .waddr    (waddr),
+      .data_in  (data_in),
+      .rclk    (clk),
+      .ren    (ren),
+      .raddr    (raddr),
+      .data_out    (data_out) );
+
+endmodule