Update Readme

README.md

@@ -1,23 +1,28 @@
-# Getting Started with FPGA-SPICE
+# Getting Started with OpenFPGA
 
 [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA)
 [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)
 
 ## Introduction
 
-FPGA-SPICE is an extension to VPR. It is an IP Verilog Generator allowing reliable and fast testing of heterogeneous architectures.
+OpenFPGA is an extension to VPR. It is an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.
 
 ## Compilation
 
 The different ways of compiling can be found in the **./compilation** folder.
 
-We currently implemented it for:
+**Compilation steps:**
+1. Create a folder named build in OpenPFGA repository (mkdir build && cd build)
+2. Create Makefile in this folder using cmake (cmake ..)
+3. Compile the tool and its dependencies (make)
 
-1. Ubuntu 18.04
-2. Red Hat 7.5
-3. MacOS High Sierra 10.13.4
+*We currently implemented OpenFPGA for:*
 
-Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.
+*1. Ubuntu 18.04*
+*2. Red Hat 7.5*
+*3. MacOS High Sierra 10.13.4*
+
+*Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.*
 
 ## Documentation
 OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) includes tutorials, descriptions of the design flow, and tool options.

compilation/macos_compilation.md

@@ -32,9 +32,9 @@ This will show the different options that can be used. Our modifications concern
 
 A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog
 
-`source ./go.sh`
+`source ./go_fpga_verilog.sh`
 
-This script uses the enhanced version of vpr with some new options such as --fpga_spice_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
+This script uses the enhanced version of vpr with some new options such as --fpga_verilog_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
 For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html).
 
 As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture.

compilation/red_hat_compilation.md

@@ -32,9 +32,9 @@ This will show the different options that can be used. Our modifications concern
 
 A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog
 
-`source ./go.sh`
+`source ./go_fpga_verilog.sh`
 
-This script uses the enhanced version of vpr with some new options such as --fpga_spice_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
+This script uses the enhanced version of vpr with some new options such as --fpga_verilog_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
 For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html).
 
 As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture.

compilation/ubuntu_compilation.md

@@ -29,9 +29,9 @@ This will show the different options that can be used. Our modifications concern
 
 A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog
 
-`source ./go.sh`
+`source ./go_fpga_verilog.sh`
 
-This script uses the enhanced version of vpr with some new options such as --fpga_spice_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
+This script uses the enhanced version of vpr with some new options such as --fpga_verilog_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
 For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html).
 
 As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture.

docs/source/fpga_verilog/command_line_usage.rst

@@ -20,7 +20,7 @@ FPGA-Verilog Supported Options::
    :widths: 15, 30
 
    "--fpga_verilog", "Turn on the FPGA-Verilog."
-   "--fpga_verilog_dir <dir_path>", "Specify the directory that all the Verilog files will be outputted to. <dir_path> is the destination directory."
+   "--fpga_verilog_dir <dir_path>", "Specify the directory that all the Verilog files will be outputted to <dir_path> is the destination directory."
    "--fpga_verilog_include_timing", "Includes the timings found in the XML file."
    "--fpga_verilog_init_sim", "Initializes the simulation for ModelSim."
    "--fpga_verilog_print_modelsim_autodeck", "Generates the scripts necessary to the ModelSim simulation."