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clean up warnings in SDC pb_type generator

This commit is contained in:
tangxifan 2019-05-24 15:23:38 -06:00
parent 924136e7a2
commit 27c234711e
2 changed files with 54 additions and 69 deletions
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93
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c
View File

@ -74,13 +74,10 @@ void sdc_dump_annotation(char* from_path, // includes the cell
return; return;
} }
void dump_sdc_pb_graph_pin_interc(FILE* fp,
void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, t_pb_graph_pin* des_pb_graph_pin,
FILE* fp, t_mode* cur_mode,
enum e_spice_pin2pin_interc_type pin2pin_interc_type, char* instance_name) {
t_pb_graph_pin* des_pb_graph_pin,
t_mode* cur_mode,
char* instance_name) {
int iedge; int iedge;
int fan_in = 0; int fan_in = 0;
t_interconnect* cur_interc = NULL; t_interconnect* cur_interc = NULL;
@ -284,12 +281,11 @@ void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
/* Print the SPICE interconnections of a port defined in pb_graph */ /* Print the SPICE interconnections of a port defined in pb_graph */
void dump_sdc_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, void dump_sdc_pb_graph_port_interc(FILE* fp,
FILE* fp, t_pb_graph_node* cur_pb_graph_node,
t_pb_graph_node* cur_pb_graph_node, enum e_spice_pb_port_type pb_port_type,
enum e_spice_pb_port_type pb_port_type, t_mode* cur_mode,
t_mode* cur_mode, char* instance_name) {
char* instance_name) {
int iport, ipin; int iport, ipin;
/* Check the file handler*/ /* Check the file handler*/
@ -305,36 +301,30 @@ void dump_sdc_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info,
for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) {
/* If this is a idle block, we set 0 to the selected edge*/ /* If this is a idle block, we set 0 to the selected edge*/
/* Get the selected edge of current pin*/ /* Get the selected edge of current pin*/
dump_sdc_pb_graph_pin_interc (cur_sram_orgz_info, dump_sdc_pb_graph_pin_interc (fp,
fp, &(cur_pb_graph_node->input_pins[iport][ipin]),
INPUT2INPUT_INTERC, cur_mode,
&(cur_pb_graph_node->input_pins[iport][ipin]), instance_name);
cur_mode,
instance_name);
} }
} }
break; break;
case SPICE_PB_PORT_OUTPUT: case SPICE_PB_PORT_OUTPUT:
for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) {
for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) {
dump_sdc_pb_graph_pin_interc(cur_sram_orgz_info, dump_sdc_pb_graph_pin_interc(fp,
fp, &(cur_pb_graph_node->output_pins[iport][ipin]),
OUTPUT2OUTPUT_INTERC, cur_mode,
&(cur_pb_graph_node->output_pins[iport][ipin]), instance_name);
cur_mode,
instance_name);
} }
} }
break; break;
case SPICE_PB_PORT_CLOCK: case SPICE_PB_PORT_CLOCK:
for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) {
for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) {
dump_sdc_pb_graph_pin_interc(cur_sram_orgz_info, dump_sdc_pb_graph_pin_interc(fp,
fp, &(cur_pb_graph_node->clock_pins[iport][ipin]),
INPUT2INPUT_INTERC, cur_mode,
&(cur_pb_graph_node->clock_pins[iport][ipin]), instance_name);
cur_mode,
instance_name);
} }
} }
break; break;
@ -347,11 +337,10 @@ void dump_sdc_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info,
return; return;
} }
void sdc_dump_cur_node_constraints(t_sram_orgz_info* cur_sram_orgz_info, void sdc_dump_cur_node_constraints(FILE* fp,
FILE* fp, t_pb_graph_node* cur_pb_graph_node,
t_pb_graph_node* cur_pb_graph_node, int select_mode_index,
int select_mode_index, char* instance_name) {
char* instance_name) {
int ipb, jpb; int ipb, jpb;
t_mode* cur_mode = NULL; t_mode* cur_mode = NULL;
t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type;
@ -381,11 +370,11 @@ void sdc_dump_cur_node_constraints(t_sram_orgz_info* cur_sram_orgz_info,
* | * |
* input_pins, edges, output_pins * input_pins, edges, output_pins
*/ */
dump_sdc_pb_graph_port_interc(cur_sram_orgz_info, fp, dump_sdc_pb_graph_port_interc(fp,
cur_pb_graph_node, cur_pb_graph_node,
SPICE_PB_PORT_OUTPUT, SPICE_PB_PORT_OUTPUT,
cur_mode, cur_mode,
instance_name); instance_name);
/* We check input_pins of child_pb_graph_node and its the input_edges /* We check input_pins of child_pb_graph_node and its the input_edges
* Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node
@ -398,17 +387,17 @@ void sdc_dump_cur_node_constraints(t_sram_orgz_info* cur_sram_orgz_info,
for (jpb = 0; jpb < cur_pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { for (jpb = 0; jpb < cur_pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) {
child_pb_graph_node = &(cur_pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]); child_pb_graph_node = &(cur_pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]);
/* For each child_pb_graph_node input pins*/ /* For each child_pb_graph_node input pins*/
dump_sdc_pb_graph_port_interc(cur_sram_orgz_info, fp, dump_sdc_pb_graph_port_interc(fp,
child_pb_graph_node, child_pb_graph_node,
SPICE_PB_PORT_INPUT, SPICE_PB_PORT_INPUT,
cur_mode, cur_mode,
instance_name); instance_name);
/* TODO: for clock pins, we should do the same work */ /* TODO: for clock pins, we should do the same work */
dump_sdc_pb_graph_port_interc(cur_sram_orgz_info, fp, dump_sdc_pb_graph_port_interc(fp,
child_pb_graph_node, child_pb_graph_node,
SPICE_PB_PORT_CLOCK, SPICE_PB_PORT_CLOCK,
cur_mode, cur_mode,
instance_name); instance_name);
} }
} }
return; return;
@ -449,7 +438,7 @@ void sdc_rec_dump_child_pb_graph_node(t_sram_orgz_info* cur_sram_orgz_info,
sdc_rec_dump_child_pb_graph_node(cur_sram_orgz_info, fp, &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), instance_name); sdc_rec_dump_child_pb_graph_node(cur_sram_orgz_info, fp, &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), instance_name);
} }
} }
sdc_dump_cur_node_constraints(cur_sram_orgz_info, fp, cur_pb_graph_node, mode_index, instance_name); // graph_head only has one pb_type sdc_dump_cur_node_constraints(fp, cur_pb_graph_node, mode_index, instance_name); // graph_head only has one pb_type
} }
return; return;

30
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.h
View File

@ -4,25 +4,21 @@ void sdc_dump_annotation(char* from_path, // includes the cell
FILE* fp, FILE* fp,
t_pb_graph_edge* cur_edge); t_pb_graph_edge* cur_edge);
void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, void dump_sdc_pb_graph_pin_interc(FILE* fp,
FILE* fp, t_pb_graph_pin* des_pb_graph_pin,
enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_mode* cur_mode,
t_pb_graph_pin* des_pb_graph_pin, char* instance_name);
t_mode* cur_mode,
char* instance_name);
void dump_sdc_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, void dump_sdc_pb_graph_port_interc(FILE* fp,
FILE* fp, t_pb_graph_node* cur_pb_graph_node,
t_pb_graph_node* cur_pb_graph_node, enum e_spice_pb_port_type pb_port_type,
enum e_spice_pb_port_type pb_port_type, t_mode* cur_mode,
t_mode* cur_mode, char* instance_name);
char* instance_name);
void sdc_dump_cur_node_constraints(t_sram_orgz_info* cur_sram_orgz_info, void sdc_dump_cur_node_constraints(FILE* fp,
FILE* fp, t_pb_graph_node* cur_pb_graph_node,
t_pb_graph_node* cur_pb_graph_node, int select_mode_index,
int select_mode_index, char* instance_name);
char* instance_name);
void sdc_rec_dump_child_pb_graph_node(t_sram_orgz_info* cur_sram_orgz_info, void sdc_rec_dump_child_pb_graph_node(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp, FILE* fp,