From 27b8007d1b67cceafa4f84ed91e74d45dbed3c99 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 27 May 2023 12:45:29 -0700 Subject: [PATCH] [test] rework pcf support testcase for mock wrapper --- .../mock_wrapper_example_script.openfpga | 2 +- .../mock_wrapper_bgf/config/task.conf | 1 + .../config/task.conf | 1 + .../config/task.conf | 1 + .../config/and2_latch_pin_constraints.xml | 11 +++++++++++ .../config/repack_pin_constraints.xml | 14 ++++++++++++++ .../mock_wrapper_pcf/config/task.conf | 17 +++++++---------- 7 files changed, 36 insertions(+), 11 deletions(-) create mode 100644 openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/and2_latch_pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/repack_pin_constraints.xml diff --git a/openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga index 90eae6d4e..feed9d0e7 100644 --- a/openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga @@ -30,7 +30,7 @@ write_fabric_hierarchy --file ./fabric_hierarchy.txt # Repack the netlist to physical pbs # This must be done before bitstream generator and testbench generation # Strongly recommend it is done after all the fix-up have been applied -repack #--verbose +repack ${OPENFPGA_REPACK_DESIGN_CONSTRAINTS} #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_bgf/config/task.conf b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_bgf/config/task.conf index 93e225201..1b5e4a371 100644 --- a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_bgf/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_bgf/config/task.conf @@ -19,6 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_design_constraints= openfpga_mock_wrapper_options=--explicit_port_mapping openfpga_mock_wrapper_bgf= openfpga_mock_wrapper_pcf= diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_explicit_port_mapping/config/task.conf b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_explicit_port_mapping/config/task.conf index 1aa6907ce..ce8a09b7f 100644 --- a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_explicit_port_mapping/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_explicit_port_mapping/config/task.conf @@ -19,6 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_design_constraints= openfpga_mock_wrapper_options=--explicit_port_mapping openfpga_mock_wrapper_bgf= openfpga_mock_wrapper_pcf= diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_implicit_port_mapping/config/task.conf b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_implicit_port_mapping/config/task.conf index 87008c7f5..6e6d87b9f 100644 --- a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_implicit_port_mapping/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_implicit_port_mapping/config/task.conf @@ -19,6 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_design_constraints= openfpga_mock_wrapper_options= openfpga_mock_wrapper_bgf= openfpga_mock_wrapper_pcf= diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/and2_latch_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/and2_latch_pin_constraints.xml new file mode 100644 index 000000000..e6949c9d4 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/and2_latch_pin_constraints.xml @@ -0,0 +1,11 @@ + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/repack_pin_constraints.xml new file mode 100644 index 000000000..d695cf85e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/repack_pin_constraints.xml @@ -0,0 +1,14 @@ + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/task.conf index 87008c7f5..f1370d2fe 100644 --- a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/task.conf @@ -17,27 +17,24 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4Clk_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_4clock_sim_openfpga.xml +openfpga_repack_design_constraints=--design_constraints ${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_mock_wrapper_options= openfpga_mock_wrapper_bgf= openfpga_mock_wrapper_pcf= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v -bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch_2clock/and2_latch_2clock.v [SYNTHESIS_PARAM] bench_read_verilog_options_common = -nolatches -bench0_top = and2 -bench1_top = or2 - -bench2_top = and2_latch +bench1_top = and2_latch_2clock +bench1_openfpga_pin_constraints=--design_constraints ${PATH:TASK_DIR}/config/and2_latch_pin_constraints.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test=