From 27a480b5f8c6bba8a72428f6c235c0141fa8ff32 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 17:45:54 -0700 Subject: [PATCH] [Test] arch name fix in the test case --- .../global_tile_ports/global_tile_reset/config/task.conf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf index d1fa21689..8fb18383e 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf @@ -17,11 +17,11 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClkReset_cc_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClkReset_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v