start refactoring bitstream generation

vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.cpp

@@ -0,0 +1,46 @@
+/******************************************************************************
+ * This file includes member functions for data structure BitstreamContext 
+ ******************************************************************************/
+#include "vtr_assert.h"
+#include "bitstream_context.h"
+
+/**************************************************
+ * Public Accessors : Aggregates
+ *************************************************/
+/* Find all the configuration bits */
+BitstreamContext::config_bit_range BitstreamContext::bits() const {
+  return vtr::make_range(bit_ids_.begin(), bit_ids_.end());
+}
+
+/******************************************************************************
+ * Public Accessors
+ ******************************************************************************/
+bool BitstreamContext::bit_value(const ConfigBitId& bit_id) const {
+  /* Ensure a valid id */
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+
+  return bit_values_[bit_id];
+}
+
+
+/******************************************************************************
+ * Public Mutators
+ ******************************************************************************/
+ConfigBitId BitstreamContext::add_bit(const bool& bit_value) {
+  ConfigBitId bit = ConfigBitId(bit_ids_.size());
+  /* Add a new bit, and allocate associated data structures */
+  bit_ids_.push_back(bit);
+  bit_values_.push_back(bit_value);
+  shared_config_bit_values_.emplace_back();
+  bit_parent_modules_.emplace_back();
+  bit_parent_instances_.emplace_back();
+
+  return bit; 
+}
+
+/******************************************************************************
+ * Public Validators
+ ******************************************************************************/
+bool BitstreamContext::valid_bit_id(const ConfigBitId& bit_id) const {
+  return (size_t(bit_id) < bit_ids_.size()) && (bit_id == bit_ids_[bit_id]);
+}

vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h

@@ -4,27 +4,54 @@
 #ifndef BITSTREAM_CONTEXT_H
 #define BITSTREAM_CONTEXT_H
 
+#include <vector>
 #include "vtr_vector.h"
+#include "module_manager.h"
+
 #include "bitstream_context_fwd.h"
 
 class BitstreamContext {
-  private: /* Internal data */
-    enum e_sram_orgz config_scheme_;  /* The type of configuration protocol */
-    CircuitModelId& sram_model_;      /* The memory circuit model used by the Bitstream generation */
-    size_t num_memory_bits_;          /* Number of memory bits */ 
-    size_t num_bls_;                  /* Number of Bit Lines */
-    size_t num_wls_;                  /* Number of Word Lines */
+  public: /* Types and ranges */
+    typedef vtr::vector<ConfigBitId, ConfigBitId>::const_iterator config_bit_iterator;
+
+    typedef vtr::Range<config_bit_iterator> config_bit_range;
+
+  public: /* Public aggregators */
+    /* Find all the configuration bits */
+    config_bit_range bits() const;
+
+  public:  /* Public Accessors */
+    bool bit_value(const ConfigBitId& bit_id) const;
+
+  public:  /* Public Mutators */
+    ConfigBitId add_bit(const bool& bit_value);
+
+  public:  /* Public Validators */
+    bool valid_bit_id(const ConfigBitId& bit_id) const;
+
+  private: /* Internal data */
+    size_t num_shared_bits_;         /* Number of reserved Bit/WL Lines, ONLY applicable to RRAM-based FPGA */
 
-    size_t num_reserved_bls_;         /* Number of reserved Bit Lines, ONLY applicable to RRAM-based FPGA */
-    size_t num_reserved_wls_;         /* Number of reserved Word Lines, ONLY applicable to RRAM-based FPGA  */
     /* Unique id of a bit in the Bitstream */
     vtr::vector<ConfigBitId, ConfigBitId> bit_ids_; 
-    /* Bit line address of a bit in the Bitream: ONLY applicable to memory-decoders */
-    vtr::vector<ConfigBitId, size_t> bl_addr_;     
-    /* Word line address of a bit in the Bitream: ONLY applicable to memory-decoders */
-    vtr::vector<ConfigBitId, size_t> wl_addr_;     
-    /* value of a bit in the Bitream */
-    vtr::vector<ConfigBitId, bool> bit_val_;
+    /* value of a bit in the Bitstream */
+    vtr::vector<ConfigBitId, bool> bit_values_;
+    /* value of a shared configuration bits in the Bitstream */
+    vtr::vector<ConfigBitId, std::vector<bool>> shared_config_bit_values_;
+
+    /* Back-annotation for the bits */
+    /* Parent Module of a bit in the Bitstream 
+     * For each bit, the list of ModuleId and instance ids reflect its position in the module tree
+     * The first ModuleId/Instance is the direct parent module/instance of the bit 
+     * while the last ModuleId/instance is the top-level module/instance of the bit
+     * For example: a bit could be back traced by
+     * <LastModuleId>[<LastInstanceId>]/.../<FirstModuleId>[<FirstInstanceId>]
+     */
+    vtr::vector<ConfigBitId, std::vector<ModuleId>> bit_parent_modules_;
+    vtr::vector<ConfigBitId, std::vector<size_t>> bit_parent_instances_;
+
+    /* Fast lookup for bitstream */
+    std::map<std::string, ConfigBitId> bit_lookup_;
 };
 
 #endif

vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h

@@ -1,14 +1,14 @@
 /**************************************************
  * This file includes only declarations for 
- * the data structures for module managers
- * Please refer to module_manager.h for more details
+ * the data structures for bitstream database
+ * Please refer to bitstream_context.h for more details
  *************************************************/
-#ifndef MODULE_MANAGER_FWD_H
-#define MODULE_MANAGER_FWD_H
+#ifndef BITSTREAM_CONTEXT_FWD_H
+#define BITSTREAM_CONTEXT_MANAGER_FWD_H
 
 #include "vtr_strong_id.h"
 
-/* Strong Ids for ModuleManager */
+/* Strong Ids for BitstreamContext */
 struct config_bit_id_tag;
 
 typedef vtr::StrongId<config_bit_id_tag> ConfigBitId;