diff --git a/.travis/script.sh b/.travis/script.sh
index 60c3d0715..ac801729c 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -105,6 +105,12 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/duplicated_grid_pi
 echo -e "Testing Verilog generation with spy output pads";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/spypad --debug --show_thread_logs
 
+echo -e "Testing fabric Verilog generation only";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_fabric --debug --show_thread_logs
+
+echo -e "Testing Verilog testbench generation only";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_testbench --debug --show_thread_logs
+
 # Verify MCNC big20 benchmark suite with ModelSim 
 # Please make sure you have ModelSim installed in the environment
 # Otherwise, it will fail