riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Test] Update regression test cases for fpga verilog

This commit is contained in:
tangxifan 2021-02-28 12:24:36 -07:00
parent ff29cc3dff
commit 27200e3daa
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
View File

@ -93,13 +93,13 @@ echo -e "Testing Verilog generation with routing multiplexers without constant i
run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
echo -e "Testing Verilog generation with behavioral description"; echo -e "Testing Verilog generation with behavioral description";
run-task fpga_verilog/behavioral_verilog --debug --show_thread_logs run-task fpga_verilog/verilog_netlist_formats/behavioral_verilog --debug --show_thread_logs
echo -e "Testing synthesizable Verilog generation with external standard cells"; echo -e "Testing synthesizable Verilog generation with external standard cells";
run-task fpga_verilog/synthesizable_verilog --debug --show_thread_logs run-task fpga_verilog/verilog_netlist_formats/synthesizable_verilog --debug --show_thread_logs
echo -e "Testing implicit Verilog generation"; echo -e "Testing implicit Verilog generation";
run-task fpga_verilog/implicit_verilog --debug --show_thread_logs run-task fpga_verilog/verilog_netlist_formats/implicit_verilog --debug --show_thread_logs
echo -e "Testing Verilog generation with flatten routing modules"; echo -e "Testing Verilog generation with flatten routing modules";
run-task fpga_verilog/flatten_routing --debug --show_thread_logs run-task fpga_verilog/flatten_routing --debug --show_thread_logs