diff --git a/openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga
index feed9d0e7..b1095060b 100644
--- a/openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga
@@ -22,6 +22,7 @@ lut_truth_table_fixup
 #  - Enabled compression on routing architecture modules
 #  - Enable pin duplication on grid modules
 build_fabric --compress_routing #--verbose
+${OPENFPGA_MOCK_WRAPPER_ADD_FPGA_CORE}
 
 # Write the fabric hierarchy of module graph to a file
 # This is used by hierarchical PnR flows
@@ -44,7 +45,7 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
-write_mock_fpga_wrapper --file ./SRC ${OPENFPGA_MOCK_WRAPPER_OPTIONS} ${OPENFPGA_MOCK_WRAPPER_BGF} ${OPENFPGA_MOCK_WRAPPER_PCF}
+write_mock_fpga_wrapper --file ./SRC ${OPENFPGA_MOCK_WRAPPER_OPTIONS} ${OPENFPGA_MOCK_WRAPPER_BGF} ${OPENFPGA_MOCK_WRAPPER_PCF} 
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists
diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_bgf/config/task.conf b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_bgf/config/task.conf
index 1b5e4a371..ed90fa347 100644
--- a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_bgf/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_bgf/config/task.conf
@@ -23,6 +23,7 @@ openfpga_repack_design_constraints=
 openfpga_mock_wrapper_options=--explicit_port_mapping
 openfpga_mock_wrapper_bgf=
 openfpga_mock_wrapper_pcf=
+openfpga_mock_wrapper_add_fpga_core=
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_explicit_port_mapping/config/task.conf b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_explicit_port_mapping/config/task.conf
index ce8a09b7f..efda62297 100644
--- a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_explicit_port_mapping/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_explicit_port_mapping/config/task.conf
@@ -23,6 +23,7 @@ openfpga_repack_design_constraints=
 openfpga_mock_wrapper_options=--explicit_port_mapping
 openfpga_mock_wrapper_bgf=
 openfpga_mock_wrapper_pcf=
+openfpga_mock_wrapper_add_fpga_core=
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_fpga_core/config/counter8_bus_group.xml b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_fpga_core/config/counter8_bus_group.xml
new file mode 100644
index 000000000..a0fd22f77
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_fpga_core/config/counter8_bus_group.xml
@@ -0,0 +1,12 @@
+<bus_group>
+  <bus name="result[7:0]" big_endian="false">
+    <pin id="0" name="result_0_"/>
+    <pin id="1" name="result_1_"/>
+    <pin id="2" name="result_2_"/>
+    <pin id="3" name="result_3_"/>
+    <pin id="4" name="result_4_"/>
+    <pin id="5" name="result_5_"/>
+    <pin id="6" name="result_6_"/>
+    <pin id="7" name="result_7_"/>
+  </bus>
+</bus_group>
diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_fpga_core/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_fpga_core/config/pin_constraints_reset.xml
new file mode 100644
index 000000000..abcf209f6
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_fpga_core/config/pin_constraints_reset.xml
@@ -0,0 +1,7 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="reset"/>
+</pin_constraints>
+
diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_fpga_core/config/task.conf b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_fpga_core/config/task.conf
new file mode 100644
index 000000000..9647f9374
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_fpga_core/config/task.conf
@@ -0,0 +1,52 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_repack_design_constraints=
+openfpga_mock_wrapper_options=--explicit_port_mapping
+openfpga_mock_wrapper_bgf=
+openfpga_mock_wrapper_pcf=
+openfpga_mock_wrapper_add_fpga_core=add_fpga_core_to_fabric --io_naming ${PATH:TASK_DIR}/config/wrapper_io_naming.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v
+bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v
+bench_yosys_bram_map_rules_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt
+bench_yosys_bram_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v
+bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v
+bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
+
+bench0_top = counter
+bench0_openfpga_mock_wrapper_pcf=-pcf ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
+bench0_openfpga_mock_wrapper_bgf=-bgf ${PATH:TASK_DIR}/config/counter8_bus_group.xml
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_fpga_core/config/wrapper_io_naming.xml b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_fpga_core/config/wrapper_io_naming.xml
new file mode 100644
index 000000000..616ce00dd
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_fpga_core/config/wrapper_io_naming.xml
@@ -0,0 +1,11 @@
+<ports>
+  <port top_name="pclk" core_name="prog_clk"/> 
+  <port top_name="top_io[0:7]" core_name="gfpga_pad_GPIO_PAD[0:7]"/> 
+  <port top_name="right_ioA[0:3]" core_name="gfpga_pad_GPIO_PAD[8:11]"/> 
+  <port top_name="right_ioB[0:3]" core_name="gfpga_pad_GPIO_PAD[12:15]"/> 
+  <port top_name="bottom_io[0:7]" core_name="gfpga_pad_GPIO_PAD[16:23]"/> 
+  <port top_name="left_io[0:7]" core_name="gfpga_pad_GPIO_PAD[24:31]"/> 
+  <port top_name="config_head" core_name="ccff_head"/> 
+  <port top_name="config_tail" core_name="ccff_tail"/> 
+  <port top_name="pvt_sensor" is_dummy="true" direction="input"/>
+</ports>
diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_implicit_port_mapping/config/task.conf b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_implicit_port_mapping/config/task.conf
index 6e6d87b9f..e05f55e87 100644
--- a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_implicit_port_mapping/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_implicit_port_mapping/config/task.conf
@@ -23,6 +23,7 @@ openfpga_repack_design_constraints=
 openfpga_mock_wrapper_options=
 openfpga_mock_wrapper_bgf=
 openfpga_mock_wrapper_pcf=
+openfpga_mock_wrapper_add_fpga_core=
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/task.conf
index 3352a51bf..3e2a95a3a 100644
--- a/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/mock_wrapper/mock_wrapper_pcf/config/task.conf
@@ -23,6 +23,7 @@ openfpga_repack_design_constraints=--design_constraints ${PATH:TASK_DIR}/config/
 openfpga_mock_wrapper_options=
 openfpga_mock_wrapper_bgf=
 openfpga_mock_wrapper_pcf=
+openfpga_mock_wrapper_add_fpga_core=
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml