From 264dc8458de73bb2561a3b13ab4a354c8f27d798 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 15 Jan 2020 20:21:53 -0700 Subject: [PATCH] add XML parsing for delay matrix in circuit model --- .../libarchopenfpga/src/circuit_library.cpp | 14 ++--- .../libarchopenfpga/src/circuit_library.h | 16 +++--- .../libarchopenfpga/src/circuit_types.h | 2 +- .../src/read_xml_circuit_library.cpp | 55 ++++++++++++++++++- 4 files changed, 70 insertions(+), 17 deletions(-) diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index 567f661ec..3c68583a5 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -904,7 +904,7 @@ size_t CircuitLibrary::timing_edge_sink_pin(const CircuitEdgeId& edge) const { return edge_sink_pin_ids_[edge]; } -float CircuitLibrary::timing_edge_delay(const CircuitEdgeId& edge, const enum circuit_model_delay_type& delay_type) const { +float CircuitLibrary::timing_edge_delay(const CircuitEdgeId& edge, const enum e_circuit_model_delay_type& delay_type) const { /* Validate the edge id */ VTR_ASSERT_SAFE(valid_edge_id(edge)); return edge_timing_info_[edge][delay_type]; @@ -1421,7 +1421,7 @@ void CircuitLibrary::set_port_sram_orgz(const CircuitPortId& circuit_port_id, * if no, resize and assign values */ void CircuitLibrary::add_delay_info(const CircuitModelId& model_id, - const enum circuit_model_delay_type& delay_type) { + const enum e_circuit_model_delay_type& delay_type) { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); /* Check the range of vector */ @@ -1437,7 +1437,7 @@ void CircuitLibrary::add_delay_info(const CircuitModelId& model_id, } void CircuitLibrary::set_delay_in_port_names(const CircuitModelId& model_id, - const enum circuit_model_delay_type& delay_type, + const enum e_circuit_model_delay_type& delay_type, const std::string& in_port_names) { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); @@ -1448,7 +1448,7 @@ void CircuitLibrary::set_delay_in_port_names(const CircuitModelId& model_id, } void CircuitLibrary::set_delay_out_port_names(const CircuitModelId& model_id, - const enum circuit_model_delay_type& delay_type, + const enum e_circuit_model_delay_type& delay_type, const std::string& out_port_names) { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); @@ -1459,7 +1459,7 @@ void CircuitLibrary::set_delay_out_port_names(const CircuitModelId& model_id, } void CircuitLibrary::set_delay_values(const CircuitModelId& model_id, - const enum circuit_model_delay_type& delay_type, + const enum e_circuit_model_delay_type& delay_type, const std::string& delay_values) { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); @@ -1992,7 +1992,7 @@ void CircuitLibrary::add_edge(const CircuitModelId& model_id, void CircuitLibrary::set_edge_delay(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id, - const enum circuit_model_delay_type& delay_type, + const enum e_circuit_model_delay_type& delay_type, const float& delay_value) { /* validate the circuit_edge_id */ VTR_ASSERT(valid_circuit_edge_id(circuit_edge_id)); @@ -2174,7 +2174,7 @@ bool CircuitLibrary::valid_edge_id(const CircuitEdgeId& edge_id) const { return ( size_t(edge_id) < edge_ids_.size() ) && ( edge_id == edge_ids_[edge_id] ); } -bool CircuitLibrary::valid_delay_type(const CircuitModelId& model_id, const enum circuit_model_delay_type& delay_type) const { +bool CircuitLibrary::valid_delay_type(const CircuitModelId& model_id, const enum e_circuit_model_delay_type& delay_type) const { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); return ( size_t(delay_type) < delay_types_[model_id].size() ) && ( delay_type == delay_types_[model_id][size_t(delay_type)] ); diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.h b/libopenfpga/libarchopenfpga/src/circuit_library.h index 38eb99a03..0005b9058 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.h +++ b/libopenfpga/libarchopenfpga/src/circuit_library.h @@ -266,7 +266,7 @@ class CircuitLibrary { size_t timing_edge_src_pin(const CircuitEdgeId& edge) const; CircuitPortId timing_edge_sink_port(const CircuitEdgeId& edge) const; size_t timing_edge_sink_pin(const CircuitEdgeId& edge) const; - float timing_edge_delay(const CircuitEdgeId& edge, const enum circuit_model_delay_type& delay_type) const; + float timing_edge_delay(const CircuitEdgeId& edge, const enum e_circuit_model_delay_type& delay_type) const; public: /* Public Accessors: Methods to find circuit model */ CircuitModelId model(const char* name) const; CircuitModelId model(const std::string& name) const; @@ -346,15 +346,15 @@ class CircuitLibrary { const enum e_sram_orgz& sram_orgz); /* Delay information */ void add_delay_info(const CircuitModelId& model_id, - const enum circuit_model_delay_type& delay_type); + const enum e_circuit_model_delay_type& delay_type); void set_delay_in_port_names(const CircuitModelId& model_id, - const enum circuit_model_delay_type& delay_type, + const enum e_circuit_model_delay_type& delay_type, const std::string& in_port_names); void set_delay_out_port_names(const CircuitModelId& model_id, - const enum circuit_model_delay_type& delay_type, + const enum e_circuit_model_delay_type& delay_type, const std::string& out_port_names); void set_delay_values(const CircuitModelId& model_id, - const enum circuit_model_delay_type& delay_type, + const enum e_circuit_model_delay_type& delay_type, const std::string& delay_values); /* Buffer/Inverter-related parameters */ void set_buffer_type(const CircuitModelId& model_id, @@ -429,7 +429,7 @@ class CircuitLibrary { const CircuitPortId& to_port, const size_t& to_pin); void set_edge_delay(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id, - const enum circuit_model_delay_type& delay_type, + const enum e_circuit_model_delay_type& delay_type, const float& delay_value); /* validate the circuit_edge_id */ void set_timing_graph_delays(const CircuitModelId& model_id); @@ -443,7 +443,7 @@ class CircuitLibrary { private: /* Internal invalidators/validators */ /* Validators */ bool valid_edge_id(const CircuitEdgeId& edge_id) const; - bool valid_delay_type(const CircuitModelId& model_id, const enum circuit_model_delay_type& delay_type) const; + bool valid_delay_type(const CircuitModelId& model_id, const enum e_circuit_model_delay_type& delay_type) const; bool valid_circuit_edge_id(const CircuitEdgeId& circuit_edge_id) const; bool valid_mux_const_input_value(const size_t& const_input_value) const; /* Invalidators */ @@ -526,7 +526,7 @@ class CircuitLibrary { vtr::vector> edge_timing_info_; /* x0 => trise, x1 => tfall */ /* Delay information */ - vtr::vector> delay_types_; + vtr::vector> delay_types_; vtr::vector> delay_in_port_names_; vtr::vector> delay_out_port_names_; vtr::vector> delay_values_; diff --git a/libopenfpga/libarchopenfpga/src/circuit_types.h b/libopenfpga/libarchopenfpga/src/circuit_types.h index 3d0d8f07c..10678304b 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_types.h +++ b/libopenfpga/libarchopenfpga/src/circuit_types.h @@ -16,7 +16,7 @@ /* Header files should be included in a sequence */ /* Standard header files required go first */ -enum circuit_model_delay_type { +enum e_circuit_model_delay_type { CIRCUIT_MODEL_DELAY_RISE, CIRCUIT_MODEL_DELAY_FALL, NUM_CIRCUIT_MODEL_DELAY_TYPES diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp index c10ca5b94..ef9e4e809 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -226,6 +226,22 @@ e_wire_model_type string_to_wire_model_type(const std::string& type_string) { return NUM_WIRE_MODEL_TYPES; } +/******************************************************************** + * Convert string to the enumerate of delay model type + *******************************************************************/ +static +e_circuit_model_delay_type string_to_circuit_model_delay_type(const std::string& type_string) { + if (std::string("rise") == type_string) { + return CIRCUIT_MODEL_DELAY_RISE; + } + + if (std::string("fall") == type_string) { + return CIRCUIT_MODEL_DELAY_FALL; + } + + return NUM_CIRCUIT_MODEL_DELAY_TYPES; +} + /******************************************************************** * Parse XML codes of design technology of a circuit model to circuit library *******************************************************************/ @@ -559,6 +575,38 @@ void read_xml_wire_param(pugi::xml_node& xml_wire_param, circuit_lib.set_wire_num_levels(model, get_attribute(xml_wire_param, "num_level", loc_data).as_int(0)); } +/******************************************************************** + * This is a generic function to parse XML codes that describe + * a delay matrix for a circuit model to circuit library + *******************************************************************/ +static +void read_xml_delay_matrix(pugi::xml_node& xml_delay_matrix, + const pugiutil::loc_data& loc_data, + CircuitLibrary& circuit_lib, const CircuitModelId& model) { + /* Find the type of the delay model, so that we can add to circuit library */ + const char* type_attr = get_attribute(xml_delay_matrix, "type", loc_data).value(); + + /* Translate the type of delay matrix for a circuit model to enumerate */ + e_circuit_model_delay_type delay_type = string_to_circuit_model_delay_type(std::string(type_attr)); + + if (NUM_CIRCUIT_MODEL_DELAY_TYPES == delay_type) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_delay_matrix), + "Invalid 'type' attribute '%s'\n", + type_attr); + } + + circuit_lib.add_delay_info(model, delay_type); + + /* Parse the input ports */ + circuit_lib.set_delay_in_port_names(model, delay_type, get_attribute(xml_delay_matrix, "in_port", loc_data).as_string()); + + /* Parse the output ports */ + circuit_lib.set_delay_out_port_names(model, delay_type, get_attribute(xml_delay_matrix, "out_port", loc_data).as_string()); + + /* Parse the delay values */ + circuit_lib.set_delay_values(model, delay_type, std::string(xml_delay_matrix.child_value())); +} + /******************************************************************** * Parse XML codes of a circuit model to circuit library *******************************************************************/ @@ -679,7 +727,12 @@ void read_xml_circuit_model(pugi::xml_node& xml_model, read_xml_wire_param(xml_wire_param, loc_data, circuit_lib, model); } - /* Parse the delay matrix if defined */ + /* Parse all the delay matrix if defined */ + size_t num_delay_matrix = count_children(xml_model, "delay_matrix", loc_data, pugiutil::ReqOpt::OPTIONAL); + for (size_t idelay_matrix = 0; idelay_matrix < num_delay_matrix; ++idelay_matrix) { + auto xml_delay_matrix = get_first_child(xml_model, "delay_matrix", loc_data); + read_xml_delay_matrix(xml_delay_matrix, loc_data, circuit_lib, model); + } } /********************************************************************