From 586dd1a5103cf14e4b6ee08ee3d3975940f4fd99 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 15 Aug 2024 10:24:58 -0700 Subject: [PATCH 1/7] [test] add a new and strong test to validate the disable unused clock spines --- .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/clk_arch_1clk_1rst_3layer.xml | 72 +++++++++++++++++++ .../config/pin_constraints_reset.xml | 8 +++ .../config/pin_constraints_resetb.xml | 8 +++ .../config/repack_pin_constraints.xml | 4 ++ .../config/task.conf | 54 ++++++++++++++ 6 files changed, 147 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/clk_arch_1clk_1rst_3layer.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_reset.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_resetb.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/repack_pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/task.conf diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 9e7d8bed1..1276e8071 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -245,6 +245,7 @@ run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@ run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer $@ run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry $@ +run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup $@ diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/clk_arch_1clk_1rst_3layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/clk_arch_1clk_1rst_3layer.xml new file mode 100644 index 000000000..e7ff2bd18 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/clk_arch_1clk_1rst_3layer.xml @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3788a1411 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..1311926f5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/pin_constraints_resetb.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/task.conf new file mode 100644 index 000000000..62745b0e3 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=4x4 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_3layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options=--disable_unused_trees --disable_unused_spines + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From 00fd21704cc5052d02c028bbee12d882cd5ad402 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 15 Aug 2024 12:41:09 -0700 Subject: [PATCH 2/7] [core] fixed a bug where the switch point coordinate of src spine required adjustment --- .../src/annotation/route_clock_rr_graph.cpp | 48 ++++++++++++++----- .../build_routing_bitstream.cpp | 6 ++- 2 files changed, 41 insertions(+), 13 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 00ad3bacc..1f575d1ad 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -109,6 +109,38 @@ static int route_clock_spine_switch_point( Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); + /* Special for DEC_DIR CHANX and CHANY, there should be a offset on the source coordinate + * Note that in the following condition, the switching point occurs in switch block (x, y) + * INC CHANY (x, y + 1) + * ^ + * | + * INC CHANX (x, y) --->+<---- DEC CHANX (x + 1, y) + * | + * v + * DEC CHANY (x, y) + * + * Note that in the following condition, the switching point occurs in switch block (x, y) + * DEC CHANY (x, y + 1) + * | + * v + * DEC CHANX (x, y) <---+----> INC CHANX (x + 1, y) + * ^ + * | + * INC CHANY (x, y) + * From the user point of view, the switching point should only occur in a switch block + * So the coordinate of a switch block should be provided as the coordinate of switching point + * However, the src node and des node may not follow the switch block coordinate! + * In short, the src coordinate requires an adjustment only when + * - The src is an CHANX in DEC + * - The src is an CHANY in DEC + * No adjustment is required for des node as it always comes from the starting point of the des spine + */ + if (clk_ntwk.spine_track_type(ispine) == CHANX && src_spine_direction == Direction::DEC) { + src_coord.set_x(src_coord.x() + 1); + } + if (clk_ntwk.spine_track_type(ispine) == CHANY && src_spine_direction == Direction::DEC) { + src_coord.set_y(src_coord.y() + 1); + } RRNodeId src_node = clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, src_spine_level, ipin, src_spine_direction, verbose); @@ -160,10 +192,10 @@ static int route_clock_spine_switch_point( return CMD_EXEC_SUCCESS; /* Used internal driver, early pass */ } VTR_LOGV(verbose, - "Routed switch points of spine '%s' from (x=%lu, y=%lu) to spine " - "'%s' at (x=%lu, y=%lu)\n", - clk_ntwk.spine_name(ispine).c_str(), src_coord.x(), src_coord.y(), - clk_ntwk.spine_name(des_spine).c_str(), des_coord.x(), + "Routed switch points of spine '%s' (node '%lu') from (x=%lu, y=%lu) to spine " + "'%s' (node '%lu') at (x=%lu, y=%lu)\n", + clk_ntwk.spine_name(ispine).c_str(), size_t(src_node), src_coord.x(), src_coord.y(), + clk_ntwk.spine_name(des_spine).c_str(), size_t(des_node), des_coord.x(), des_coord.y()); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); /* It could happen that there is no net mapped some clock pin, skip the @@ -314,11 +346,8 @@ static int rec_expand_and_route_clock_spine( if (CMD_EXEC_SUCCESS != status) { return CMD_EXEC_FATAL_ERROR; } - if (curr_tap_usage) { - curr_spine_usage = true; - } /* If no taps are routed, this spine is not used. Early exit */ - if (!curr_tap_usage && clk_ntwk.is_last_level(curr_spine)) { + if (disable_unused_spines && !curr_tap_usage && clk_ntwk.is_last_level(curr_spine)) { spine_usage = false; VTR_LOGV(verbose, "Disable last-level spine '%s' as " @@ -386,9 +415,6 @@ static int rec_expand_and_route_clock_spine( /* If there are any stop is used, mark this spine is used. This is to avoid * that a spine is marked unused when only its 1st stop is actually used. * The skip condition may cause this. */ - if (curr_stop_usage) { - curr_spine_usage = true; - } /* Skip the first stop */ if (icoord == spine_coords.size() - 1) { continue; diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp index 0698b1a8c..bc6be4b7e 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp @@ -60,11 +60,14 @@ static void build_switch_block_mux_bitstream( * - There is a net mapped to cur_rr_node: we find the path id */ int path_id = DEFAULT_PATH_ID; - if (ClusterNetId::INVALID() != output_net) { + VTR_LOGV(verbose, "Prev node '%lu' for src_node '%lu'\n", size_t(routing_annotation.rr_node_prev_node(cur_rr_node)), size_t(cur_rr_node)); + AtomNetId output_atom_net = atom_ctx.lookup.atom_net(output_net); + if (true == atom_ctx.nlist.valid_net_id(output_atom_net)) { /* We must have a valid previous node that is supposed to drive the source * node! */ VTR_ASSERT(routing_annotation.rr_node_prev_node(cur_rr_node)); for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) { + VTR_LOGV(verbose, "Path: %lu -> Driver node '%lu' for src_node '%lu'\n", inode, size_t(drive_rr_nodes[inode]), size_t(cur_rr_node)); if ((input_nets[inode] == output_net) && (drive_rr_nodes[inode] == routing_annotation.rr_node_prev_node(cur_rr_node))) { @@ -135,7 +138,6 @@ static void build_switch_block_mux_bitstream( /* Add output nets */ std::string output_net_ids; - AtomNetId output_atom_net = atom_ctx.lookup.atom_net(output_net); if (true == atom_ctx.nlist.valid_net_id(output_atom_net)) { output_net_ids += atom_ctx.nlist.net_name(output_atom_net); } else { From 5877a3f7bef1a604c89d9ca2df408948012d10db Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 15 Aug 2024 12:44:03 -0700 Subject: [PATCH 3/7] [core] code format --- .../src/annotation/route_clock_rr_graph.cpp | 40 +++++++++++-------- .../build_routing_bitstream.cpp | 7 +++- 2 files changed, 28 insertions(+), 19 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 1f575d1ad..668c7ac67 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -109,9 +109,9 @@ static int route_clock_spine_switch_point( Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine); ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); - /* Special for DEC_DIR CHANX and CHANY, there should be a offset on the source coordinate - * Note that in the following condition, the switching point occurs in switch block (x, y) - * INC CHANY (x, y + 1) + /* Special for DEC_DIR CHANX and CHANY, there should be a offset on the source + * coordinate Note that in the following condition, the switching point occurs + * in switch block (x, y) INC CHANY (x, y + 1) * ^ * | * INC CHANX (x, y) --->+<---- DEC CHANX (x + 1, y) @@ -119,26 +119,30 @@ static int route_clock_spine_switch_point( * v * DEC CHANY (x, y) * - * Note that in the following condition, the switching point occurs in switch block (x, y) - * DEC CHANY (x, y + 1) + * Note that in the following condition, the switching point occurs in switch + * block (x, y) DEC CHANY (x, y + 1) * | * v * DEC CHANX (x, y) <---+----> INC CHANX (x + 1, y) * ^ * | * INC CHANY (x, y) - * From the user point of view, the switching point should only occur in a switch block - * So the coordinate of a switch block should be provided as the coordinate of switching point - * However, the src node and des node may not follow the switch block coordinate! - * In short, the src coordinate requires an adjustment only when + * From the user point of view, the switching point should only occur in a + * switch block So the coordinate of a switch block should be provided as the + * coordinate of switching point However, the src node and des node may not + * follow the switch block coordinate! In short, the src coordinate requires + * an adjustment only when * - The src is an CHANX in DEC * - The src is an CHANY in DEC - * No adjustment is required for des node as it always comes from the starting point of the des spine + * No adjustment is required for des node as it always comes from the starting + * point of the des spine */ - if (clk_ntwk.spine_track_type(ispine) == CHANX && src_spine_direction == Direction::DEC) { + if (clk_ntwk.spine_track_type(ispine) == CHANX && + src_spine_direction == Direction::DEC) { src_coord.set_x(src_coord.x() + 1); } - if (clk_ntwk.spine_track_type(ispine) == CHANY && src_spine_direction == Direction::DEC) { + if (clk_ntwk.spine_track_type(ispine) == CHANY && + src_spine_direction == Direction::DEC) { src_coord.set_y(src_coord.y() + 1); } RRNodeId src_node = clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), @@ -192,11 +196,12 @@ static int route_clock_spine_switch_point( return CMD_EXEC_SUCCESS; /* Used internal driver, early pass */ } VTR_LOGV(verbose, - "Routed switch points of spine '%s' (node '%lu') from (x=%lu, y=%lu) to spine " + "Routed switch points of spine '%s' (node '%lu') from (x=%lu, " + "y=%lu) to spine " "'%s' (node '%lu') at (x=%lu, y=%lu)\n", - clk_ntwk.spine_name(ispine).c_str(), size_t(src_node), src_coord.x(), src_coord.y(), - clk_ntwk.spine_name(des_spine).c_str(), size_t(des_node), des_coord.x(), - des_coord.y()); + clk_ntwk.spine_name(ispine).c_str(), size_t(src_node), src_coord.x(), + src_coord.y(), clk_ntwk.spine_name(des_spine).c_str(), + size_t(des_node), des_coord.x(), des_coord.y()); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); /* It could happen that there is no net mapped some clock pin, skip the * net mapping */ @@ -347,7 +352,8 @@ static int rec_expand_and_route_clock_spine( return CMD_EXEC_FATAL_ERROR; } /* If no taps are routed, this spine is not used. Early exit */ - if (disable_unused_spines && !curr_tap_usage && clk_ntwk.is_last_level(curr_spine)) { + if (disable_unused_spines && !curr_tap_usage && + clk_ntwk.is_last_level(curr_spine)) { spine_usage = false; VTR_LOGV(verbose, "Disable last-level spine '%s' as " diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp index bc6be4b7e..dd2cc7329 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp @@ -60,14 +60,17 @@ static void build_switch_block_mux_bitstream( * - There is a net mapped to cur_rr_node: we find the path id */ int path_id = DEFAULT_PATH_ID; - VTR_LOGV(verbose, "Prev node '%lu' for src_node '%lu'\n", size_t(routing_annotation.rr_node_prev_node(cur_rr_node)), size_t(cur_rr_node)); + VTR_LOGV(verbose, "Prev node '%lu' for src_node '%lu'\n", + size_t(routing_annotation.rr_node_prev_node(cur_rr_node)), + size_t(cur_rr_node)); AtomNetId output_atom_net = atom_ctx.lookup.atom_net(output_net); if (true == atom_ctx.nlist.valid_net_id(output_atom_net)) { /* We must have a valid previous node that is supposed to drive the source * node! */ VTR_ASSERT(routing_annotation.rr_node_prev_node(cur_rr_node)); for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) { - VTR_LOGV(verbose, "Path: %lu -> Driver node '%lu' for src_node '%lu'\n", inode, size_t(drive_rr_nodes[inode]), size_t(cur_rr_node)); + VTR_LOGV(verbose, "Path: %lu -> Driver node '%lu' for src_node '%lu'\n", + inode, size_t(drive_rr_nodes[inode]), size_t(cur_rr_node)); if ((input_nets[inode] == output_net) && (drive_rr_nodes[inode] == routing_annotation.rr_node_prev_node(cur_rr_node))) { From c7da894eaf2cab485977c01fe1d17631c7e418ee Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 15 Aug 2024 14:10:34 -0700 Subject: [PATCH 4/7] [core] fixed a bug where some spine was wrongly disabled --- openfpga/src/annotation/route_clock_rr_graph.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 668c7ac67..a4582b5ab 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -370,6 +370,7 @@ static int rec_expand_and_route_clock_spine( */ bool prev_stop_usage = false; if (clk_ntwk.is_last_level(curr_spine)) { + curr_spine_usage = curr_tap_usage; prev_stop_usage = curr_tap_usage; } std::reverse(spine_coords.begin(), spine_coords.end()); From 2c3584045734d608d0221d58eb08f490969341ed Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 15 Aug 2024 14:24:31 -0700 Subject: [PATCH 5/7] [test] add a new test to validate CHANY clock spin in DEC --- .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/clk_arch_1clk_1rst_2layer.xml | 32 + .../config/pin_constraints_reset.xml | 8 + .../config/pin_constraints_resetb.xml | 8 + .../config/repack_pin_constraints.xml | 4 + .../config/task.conf | 54 ++ ...frac_N4_tileable_fracff_40nm_ClkOnLeft.xml | 642 ++++++++++++++++++ 7 files changed, 749 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/clk_arch_1clk_1rst_2layer.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_reset.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_resetb.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/repack_pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/task.conf create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 1276e8071..a22bd9818 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -239,6 +239,7 @@ run-task basic_tests/global_tile_ports/global_tile_4clock_pin $@ echo -e "Testing programmable clock architecture"; run-task basic_tests/clock_network/homo_1clock_1reset_1layer_2entry $@ run-task basic_tests/clock_network/homo_1clock_2layer $@ +run-task basic_tests/clock_network/homo_1clock_2layer_dec $@ run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@ run-task basic_tests/clock_network/homo_2clock_2layer $@ run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@ diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..89f030970 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3788a1411 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..1311926f5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/pin_constraints_resetb.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/task.conf new file mode 100644 index 000000000..014465ced --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_dec/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml new file mode 100644 index 000000000..111b5709d --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm_ClkOnLeft.xml @@ -0,0 +1,642 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + clb.reset clb.clk + + clb.O[0:3] clb.I[0:5] + clb.O[4:7] clb.I[6:11] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 642cb6eb9ab88ff60e6890780a8511d1b0564b8f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 15 Aug 2024 14:28:29 -0700 Subject: [PATCH 6/7] [core] coord adjustment should occur based on des coord --- openfpga/src/annotation/route_clock_rr_graph.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index a4582b5ab..59e438a02 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -139,11 +139,11 @@ static int route_clock_spine_switch_point( */ if (clk_ntwk.spine_track_type(ispine) == CHANX && src_spine_direction == Direction::DEC) { - src_coord.set_x(src_coord.x() + 1); + src_coord.set_x(des_coord.x() + 1); } if (clk_ntwk.spine_track_type(ispine) == CHANY && src_spine_direction == Direction::DEC) { - src_coord.set_y(src_coord.y() + 1); + src_coord.set_y(des_coord.y() + 1); } RRNodeId src_node = clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree, src_spine_level, ipin, From 05ef97291108b923111e8115925d3a40e97f08d3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 15 Aug 2024 15:36:08 -0700 Subject: [PATCH 7/7] [test] typo --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index a22bd9818..b968904fb 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -239,7 +239,7 @@ run-task basic_tests/global_tile_ports/global_tile_4clock_pin $@ echo -e "Testing programmable clock architecture"; run-task basic_tests/clock_network/homo_1clock_1reset_1layer_2entry $@ run-task basic_tests/clock_network/homo_1clock_2layer $@ -run-task basic_tests/clock_network/homo_1clock_2layer_dec $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_dec $@ run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@ run-task basic_tests/clock_network/homo_2clock_2layer $@ run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@