From 2444752de89c13a27c8e68a22b099fdf79823c06 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 14:08:24 -0600
Subject: [PATCH] add untileable test case to Travis CI

---
 .travis/script.sh                             |  3 ++
 .../openfpga_shell/frac_lut/config/task.conf  |  2 +-
 .../untileable/config/task.conf               | 34 +++++++++++++++++++
 3 files changed, 38 insertions(+), 1 deletion(-)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index 754289e9f..e36520d1e 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -51,4 +51,7 @@ echo -e "Testing OpenFPGA Shell";
 echo -e "Testing Verilog generation with simple fracturable LUT6 ";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/untileable --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
index 4ea65822f..a52d2f515 100644
--- a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
@@ -18,7 +18,7 @@ fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 
 [ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
diff --git a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf
new file mode 100644
index 000000000..4ea65822f
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=