diff --git a/.travis/script.sh b/.travis/script.sh
index dc19e3582..3cc2a64b7 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -84,4 +84,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/tree_st
echo -e "Testing Verilog generation with routing mutliplexers implemented by standard cell MUX2";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/stdcell_mux2 --debug --show_thread_logs
+echo -e "Testing Verilog generation with behavioral description";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/behavioral_verilog --debug --show_thread_logs
+
end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
new file mode 100644
index 000000000..e305bbc08
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
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diff --git a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf
new file mode 100644
index 000000000..4d5f90d67
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=