diff --git a/.dockerignore b/.dockerignore index 8240dff87..83c4ab773 100644 --- a/.dockerignore +++ b/.dockerignore @@ -12,12 +12,11 @@ !/openfpga/openfpga !/vpr/libvpr.a !/vpr/vpr -!/yosys/install/share/ +!/yosys/install/share/** !/yosys/install/bin/yosys !/yosys/install/bin/yosys-abc !/yosys/install/bin/yosys-config !/yosys/install/bin/yosys-filterlib !/yosys/install/bin/yosys-smtbmc -!/openfpga_flow !/openfpga.sh -!/openfpga_flow/ +!/openfpga_flow/** diff --git a/.github/dependabot.yml b/.github/dependabot.yml new file mode 100644 index 000000000..c0e29e3f8 --- /dev/null +++ b/.github/dependabot.yml @@ -0,0 +1,21 @@ +version: 2 +updates: + - package-ecosystem: "gitsubmodule" + directory: "/" + schedule: + interval: "daily" + time: "00:00" + timezone: "America/Denver" + #assignees: + # - "username" + #labels: need to add the required label to the repo first! + # - "submodule-updates" + # must use the full team name, including the organization, as if you were @mentioning the team + reviewers: + - "tangxifan" + - "tpagarani" + # Allow dependabot to open up to 10 open pull requests. Default is 5. + # open-pull-requests-limit: 10 + allow: + # only enable for the yosys-symbiflow-plugins submodule + - dependency-name: "yosys-plugins" diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 38aa97d66..445e52ee8 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -170,12 +170,8 @@ jobs: openfpga/openfpga vpr/libvpr.a vpr/vpr - yosys/install/share/ - yosys/install/bin/yosys - yosys/install/bin/yosys-abc - yosys/install/bin/yosys-config - yosys/install/bin/yosys-filterlib - yosys/install/bin/yosys-smtbmc + yosys/install/share + yosys/install/bin openfpga_flow openfpga.sh docker_distribution: diff --git a/docs/source/contact.rst b/docs/source/contact.rst index 1e7e1e801..ae44e73f1 100644 --- a/docs/source/contact.rst +++ b/docs/source/contact.rst @@ -13,9 +13,11 @@ Technical Details about FPGA-SPICE/Verilog/Bitstream/SDC: Dr. Xifan Tang -xifan.tang@utah.edu +xifan@osfpga.org -.. Technical Details about layout auto-generation -.. Edouard Giacomin -.. edouard.giacomin@utah.edu +Technical Details about physical design + +Ganesh Gore + +ganesh.gore@utah.edu diff --git a/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh index 26a76e322..2d3bd1202 100755 --- a/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh @@ -8,14 +8,12 @@ PYTHON_EXEC=python3.8 ############################################## echo -e "QuickLogic regression tests"; -# TODO: Disabled all the tests here because Quicklogic's synthesis script is not in Yosys v0.10 release. Will bring back once Quicklogic manages to merge their contribution to Yosys upstream - echo -e "Testing yosys flow using custom ys script for running quicklogic device"; run-task quicklogic_tests/flow_test --debug --show_thread_logs -##echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device"; -##run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs -##run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs -## -##echo -e "Testing yosys flow using custom ys script for adders in quicklogic device"; -##run-task quicklogic_tests/lut_adder_test --debug --show_thread_logs +echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device"; +run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs +run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs + +echo -e "Testing yosys flow using custom ys script for adders in quicklogic device"; +run-task quicklogic_tests/lut_adder_test --debug --show_thread_logs diff --git a/yosys-plugins b/yosys-plugins index e3204198b..b48dda647 160000 --- a/yosys-plugins +++ b/yosys-plugins @@ -1 +1 @@ -Subproject commit e3204198bd50f14624d756b74f32c162dc5b0d0a +Subproject commit b48dda647aa07170b46185eff6496a2073ad0d8f