riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Update repack_option.cpp

This commit is contained in:
Yitian4Debug 2023-12-05 09:30:32 -08:00 committed by GitHub
parent 83fdaea13d
commit 231cb0f89b
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 11 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
openfpga/src/repack/repack_option.cpp
View File

@ -48,48 +48,17 @@ bool RepackOption::is_pin_ignore_global_nets(const std::string& pb_type_name,
bool RepackOption::net_is_specified_to_be_ignored(std::string cluster_net_name, bool RepackOption::net_is_specified_to_be_ignored(std::string cluster_net_name,
std::string pb_type_name, std::string pb_type_name,
const BasicPort& port) const { const BasicPort& pin) const {
auto pin_ctx_to_parse = const RepackDesignConstraints& design_constraint = design_constraints();
design_constraints_.ignore_net_on_pin(cluster_net_name); /* If found a constraint, record the net name */
if (pin_ctx_to_parse.empty()) { for (const RepackDesignConstraintId id_ :
/* Not found, return false */ design_constraint.design_constraints()) {
return false; if (design_constraint.type(id_) == RepackDesignConstraints::IGNORE_NET &&
} else { design_constraint.pb_type(id_) == pb_type_name &&
/* Split the content using a tokenizer */ design_constraint.net(id_) == cluster_net_name) {
for (auto pin_ctx_to_parse_iter : pin_ctx_to_parse) { if (design_constraint.pin(id_).mergeable(pin) &&
int num_parse_errors_temp = 0; design_constraint.pin(id_).contained(pin))
StringToken tokenizer(pin_ctx_to_parse_iter); return true;
std::vector<std::string> tokens = tokenizer.split(',');
/* Parse each token */
for (std::string token : tokens) {
/* Extract the pb_type name and port name */
StringToken pin_tokenizer(token);
std::vector<std::string> pin_info = pin_tokenizer.split('.');
/* Expect two contents, otherwise error out */
if (pin_info.size() != 2) {
std::string err_msg =
std::string("Invalid content '") + token +
std::string("' to skip, expect <pb_type_name>.<pin>\n");
VTR_LOG_ERROR(err_msg.c_str());
num_parse_errors_temp++;
continue;
}
std::string curr_pb_type_name = pin_info[0];
PortParser port_parser(pin_info[1]);
BasicPort curr_port = port_parser.port();
if (!curr_port.is_valid()) {
std::string err_msg =
std::string("Invalid pin definition '") + token +
std::string("', expect <pb_type_name>.<pin_name>[int:int]\n");
VTR_LOG_ERROR(err_msg.c_str());
num_parse_errors_temp++;
continue;
}
if (curr_port.mergeable(port) && curr_port.contained(port) &&
curr_pb_type_name == pb_type_name) {
return true;
}
}
} }
} }
return false; return false;