added pin duplication support to grid module builder
This commit is contained in:
tangxifan
parent
72d2fc6d69
commit
2306b17d9f
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@ -469,6 +469,36 @@ std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
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return port_name;
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}
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/*********************************************************************
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* Generate the port name for a grid with duplication
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* This function will generate two types of port names.
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* One with a postfix of "upper"
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* The other with a postfix of "lower"
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*********************************************************************/
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std::string generate_grid_duplicated_port_name(const size_t& height,
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const e_side& side,
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const size_t& pin_id,
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const bool& upper_port) {
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/* For non-top netlist */
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Side side_manager(side);
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std::string port_name = std::string(side_manager.to_string());
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port_name += std::string("_height_");
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port_name += std::to_string(height);
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port_name += std::string("_pin_");
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port_name += std::to_string(pin_id);
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port_name += std::string("_");
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if (true == upper_port) {
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port_name += std::string("upper");
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} else {
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VTR_ASSERT_SAFE(false == upper_port);
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port_name += std::string("lower");
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}
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return port_name;
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}
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/*********************************************************************
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* Generate the port name for a grid in the context of a module
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* To keep a short and simple name, this function will not
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@ -121,6 +121,11 @@ std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
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const size_t& pin_id,
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const bool& for_top_netlist);
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std::string generate_grid_duplicated_port_name(const size_t& height,
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const e_side& side,
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const size_t& pin_id,
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const bool& upper_port);
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std::string generate_grid_module_port_name(const size_t& pin_id);
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std::string generate_sb_module_grid_port_name(const e_side& sb_side,
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@ -8,8 +8,19 @@
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*
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* Please follow this rules when creating new features!
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*******************************************************************/
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/* External library headers */
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#include "vtr_assert.h"
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/* FPGA-X2P headers */
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#include "fpga_x2p_naming.h"
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/* Module builder headers */
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#include "build_grid_module_utils.h"
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#include "build_grid_module_duplicated_pins.h"
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/* Global variables should be the last to include */
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#include "globals.h"
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/********************************************************************
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* This function adds pb_type ports to top-level grid module with duplication
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* For each pin at each side, we create two pins which are short-wired
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@ -40,12 +51,190 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
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const ModuleId& grid_module,
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t_type_ptr grid_type_descriptor,
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const e_side& border_side) {
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/* Ensure that we have a valid grid_type_descriptor */
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VTR_ASSERT(NULL != grid_type_descriptor);
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/* Find the pin side for I/O grids*/
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std::vector<e_side> grid_pin_sides;
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/* For I/O grids, we care only one side
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* Otherwise, we will iterate all the 4 sides
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*/
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if (IO_TYPE == grid_type_descriptor) {
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grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side));
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} else {
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grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT};
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}
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/* Create a map between pin class type and grid pin direction */
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std::map<e_pin_type, ModuleManager::e_module_port_type> pin_type2type_map;
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pin_type2type_map[RECEIVER] = ModuleManager::MODULE_INPUT_PORT;
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pin_type2type_map[DRIVER] = ModuleManager::MODULE_OUTPUT_PORT;
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/* Iterate over sides, height and pins */
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for (const e_side& side : grid_pin_sides) {
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for (int iheight = 0; iheight < grid_type_descriptor->height; ++iheight) {
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for (int ipin = 0; ipin < grid_type_descriptor->num_pins; ++ipin) {
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if (1 != grid_type_descriptor->pinloc[iheight][side][ipin]) {
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continue;
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}
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/* Reach here, it means this pin is on this side */
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int class_id = grid_type_descriptor->pin_class[ipin];
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e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type;
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/* Generate the pin name */
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if (RECEIVER == pin_class_type) {
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/* For each RECEIVER PIN, we do not duplicate */
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vtr::Point<size_t> dummy_coordinate;
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std::string port_name = generate_grid_port_name(dummy_coordinate, iheight, side, ipin, false);
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BasicPort grid_port(port_name, 0, 0);
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/* Add the port to the module */
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module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]);
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} else {
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/* For each DRIVER pin, we create two copies.
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* One with a postfix of upper, indicating it is located on the upper part of a side
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* The other with a postfix of lower, indicating it is located on the lower part of a side
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*/
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VTR_ASSERT(DRIVER == pin_class_type);
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std::string upper_port_name = generate_grid_duplicated_port_name(iheight, side, ipin, true);
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BasicPort grid_upper_port(upper_port_name, 0, 0);
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/* Add the port to the module */
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module_manager.add_port(grid_module, grid_upper_port, pin_type2type_map[pin_class_type]);
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std::string lower_port_name = generate_grid_duplicated_port_name(iheight, side, ipin, false);
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BasicPort grid_lower_port(upper_port_name, 0, 0);
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/* Add the port to the module */
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module_manager.add_port(grid_module, grid_lower_port, pin_type2type_map[pin_class_type]);
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}
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}
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}
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}
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}
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/********************************************************************
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* Add module nets to connect a port of child pb_module
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* to the duplicated pins of grid module
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* Note: This function SHOULD be ONLY applied to pb_graph output pins
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* of the child module.
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* For each such pin, we connect it to two outputs of the grid module
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* one is named after "upper", and the other is named after "lower"
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*******************************************************************/
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static
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void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_manager,
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const ModuleId& grid_module,
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const ModuleId& child_module,
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const size_t& child_instance,
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t_type_ptr grid_type_descriptor,
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t_pb_graph_pin* pb_graph_pin,
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const e_side& border_side,
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const enum e_spice_pin2pin_interc_type& pin2pin_interc_type) {
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/* Make sure this is ONLY applied to output pins */
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VTR_ASSERT(OUTPUT2OUTPUT_INTERC == pin2pin_interc_type);
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/* Find the pin side for I/O grids*/
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std::vector<e_side> grid_pin_sides;
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/* For I/O grids, we care only one side
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* Otherwise, we will iterate all the 4 sides
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*/
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if (IO_TYPE == grid_type_descriptor) {
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grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side));
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} else {
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grid_pin_sides.push_back(TOP);
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grid_pin_sides.push_back(RIGHT);
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grid_pin_sides.push_back(BOTTOM);
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grid_pin_sides.push_back(LEFT);
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}
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/* num_pins/capacity = the number of pins that each type_descriptor has.
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* Capacity defines the number of type_descriptors in each grid
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* so the pin index at grid level = pin_index_in_type_descriptor
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* + type_descriptor_index_in_capacity * num_pins_per_type_descriptor
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*/
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size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster
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+ child_instance * grid_type_descriptor->num_pins / grid_type_descriptor->capacity;
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int pin_height = grid_type_descriptor->pin_height[grid_pin_index];
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for (const e_side& side : grid_pin_sides) {
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if (1 != grid_type_descriptor->pinloc[pin_height][side][grid_pin_index]) {
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continue;
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}
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/* Reach here, it means this pin is on this side */
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/* Create a net to connect the grid pin to child module pin */
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ModuleNetId net = module_manager.create_module_net(grid_module);
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/* Find the upper port in grid_module */
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std::string grid_upper_port_name = generate_grid_duplicated_port_name(pin_height, side, grid_pin_index, true);
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ModulePortId grid_module_upper_port_id = module_manager.find_module_port(grid_module, grid_upper_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_upper_port_id));
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/* Find the lower port in grid_module */
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std::string grid_lower_port_name = generate_grid_duplicated_port_name(pin_height, side, grid_pin_index, false);
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ModulePortId grid_module_lower_port_id = module_manager.find_module_port(grid_module, grid_lower_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_lower_port_id));
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/* Grid port always has only 1 pin, it is assumed when adding these ports to the module
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* if you need a change, please also change the port adding codes
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*/
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size_t grid_module_pin_id = 0;
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/* Find the port in child module */
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std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port);
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ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id));
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size_t child_module_pin_id = pb_graph_pin->pin_number;
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/* Add net sources and sinks:
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* For output-to-output connection,
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* net_source is pb_graph_pin,
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* while net_sinks are grid upper pin and grid lower pin
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*/
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module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id);
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module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_upper_port_id, grid_module_pin_id);
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module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_lower_port_id, grid_module_pin_id);
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}
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}
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/********************************************************************
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* Add module nets to connect a port of child pb_module
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* to the duplicated ports of grid module
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*******************************************************************/
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void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module_manager,
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const ModuleId& grid_module,
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const ModuleId& child_module,
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const size_t& child_instance,
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t_type_ptr grid_type_descriptor,
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const e_side& border_side) {
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/* Ensure that we have a valid grid_type_descriptor */
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VTR_ASSERT(NULL != grid_type_descriptor);
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t_pb_graph_node* top_pb_graph_node = grid_type_descriptor->pb_graph_head;
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VTR_ASSERT(NULL != top_pb_graph_node);
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for (int iport = 0; iport < top_pb_graph_node->num_input_ports; ++iport) {
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for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) {
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add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
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child_module, child_instance,
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grid_type_descriptor,
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&(top_pb_graph_node->input_pins[iport][ipin]),
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border_side,
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INPUT2INPUT_INTERC);
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}
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}
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for (int iport = 0; iport < top_pb_graph_node->num_output_ports; ++iport) {
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for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) {
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add_grid_module_net_connect_duplicated_pb_graph_pin(module_manager, grid_module,
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child_module, child_instance,
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grid_type_descriptor,
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&(top_pb_graph_node->output_pins[iport][ipin]),
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border_side,
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OUTPUT2OUTPUT_INTERC);
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}
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}
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for (int iport = 0; iport < top_pb_graph_node->num_clock_ports; ++iport) {
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for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) {
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add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
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child_module, child_instance,
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grid_type_descriptor,
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&(top_pb_graph_node->clock_pins[iport][ipin]),
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border_side,
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INPUT2INPUT_INTERC);
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}
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}
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}
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@ -0,0 +1,106 @@
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/********************************************************************
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* This file includes most utilized functions for grid module builders
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*******************************************************************/
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/* External library headers */
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#include "vtr_assert.h"
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/* FPGA-X2P headers */
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#include "fpga_x2p_naming.h"
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/* Module builder headers */
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#include "build_grid_module_utils.h"
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/* Global variables should be the last to include */
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#include "globals.h"
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/********************************************************************
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* Find the side where I/O pins locate on a grid I/O block
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* 1. I/O grids on the top side of FPGA only have ports on its bottom side
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* 2. I/O grids on the right side of FPGA only have ports on its left side
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* 3. I/O grids on the bottom side of FPGA only have ports on its top side
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* 4. I/O grids on the left side of FPGA only have ports on its right side
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*******************************************************************/
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e_side find_grid_module_pin_side(t_type_ptr grid_type_descriptor,
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const e_side& border_side) {
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VTR_ASSERT(IO_TYPE == grid_type_descriptor);
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Side side_manager(border_side);
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return side_manager.get_opposite();
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}
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/********************************************************************
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* Add module nets to connect a port of child pb_module
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* to the grid module
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*******************************************************************/
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void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager,
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const ModuleId& grid_module,
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const ModuleId& child_module,
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const size_t& child_instance,
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t_type_ptr grid_type_descriptor,
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t_pb_graph_pin* pb_graph_pin,
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const e_side& border_side,
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const enum e_spice_pin2pin_interc_type& pin2pin_interc_type) {
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/* Find the pin side for I/O grids*/
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std::vector<e_side> grid_pin_sides;
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/* For I/O grids, we care only one side
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* Otherwise, we will iterate all the 4 sides
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*/
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if (IO_TYPE == grid_type_descriptor) {
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grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side));
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} else {
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grid_pin_sides.push_back(TOP);
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grid_pin_sides.push_back(RIGHT);
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grid_pin_sides.push_back(BOTTOM);
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grid_pin_sides.push_back(LEFT);
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}
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/* num_pins/capacity = the number of pins that each type_descriptor has.
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* Capacity defines the number of type_descriptors in each grid
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* so the pin index at grid level = pin_index_in_type_descriptor
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* + type_descriptor_index_in_capacity * num_pins_per_type_descriptor
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*/
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size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster
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+ child_instance * grid_type_descriptor->num_pins / grid_type_descriptor->capacity;
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int pin_height = grid_type_descriptor->pin_height[grid_pin_index];
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for (const e_side& side : grid_pin_sides) {
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if (1 != grid_type_descriptor->pinloc[pin_height][side][grid_pin_index]) {
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continue;
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}
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/* Reach here, it means this pin is on this side */
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/* Create a net to connect the grid pin to child module pin */
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ModuleNetId net = module_manager.create_module_net(grid_module);
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/* Find the port in grid_module */
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vtr::Point<size_t> dummy_coordinate;
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std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_height, side, grid_pin_index, false);
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ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id));
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/* Grid port always has only 1 pin, it is assumed when adding these ports to the module
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* if you need a change, please also change the port adding codes
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*/
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size_t grid_module_pin_id = 0;
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/* Find the port in child module */
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std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port);
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ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id));
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size_t child_module_pin_id = pb_graph_pin->pin_number;
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/* Add net sources and sinks:
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* For input-to-input connection, net_source is grid pin, while net_sink is pb_graph_pin
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* For output-to-output connection, net_source is pb_graph_pin, while net_sink is grid pin
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*/
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switch (pin2pin_interc_type) {
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case INPUT2INPUT_INTERC:
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module_manager.add_module_net_source(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id);
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module_manager.add_module_net_sink(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id);
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break;
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case OUTPUT2OUTPUT_INTERC:
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module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id);
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module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id);
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s, [LINE%d]) Invalid pin-to-pin interconnection type!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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}
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}
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@ -0,0 +1,22 @@
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#ifndef BUILD_GRID_MODULE_UTILS_H
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#define BUILD_GRID_MODULE_UTILS_H
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#include "vpr_types.h"
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#include "sides.h"
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#include "spice_types.h"
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#include "module_manager.h"
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e_side find_grid_module_pin_side(t_type_ptr grid_type_descriptor,
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const e_side& border_side);
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void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager,
|
||||
const ModuleId& grid_module,
|
||||
const ModuleId& child_module,
|
||||
const size_t& child_instance,
|
||||
t_type_ptr grid_type_descriptor,
|
||||
t_pb_graph_pin* pb_graph_pin,
|
||||
const e_side& border_side,
|
||||
const enum e_spice_pin2pin_interc_type& pin2pin_interc_type);
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -27,24 +27,10 @@
|
|||
|
||||
/* Header files for Verilog generator */
|
||||
#include "verilog_global.h"
|
||||
#include "build_grid_module_utils.h"
|
||||
#include "build_grid_module_duplicated_pins.h"
|
||||
#include "build_grid_modules.h"
|
||||
|
||||
/********************************************************************
|
||||
* Find the side where I/O pins locate on a grid I/O block
|
||||
* 1. I/O grids on the top side of FPGA only have ports on its bottom side
|
||||
* 2. I/O grids on the right side of FPGA only have ports on its left side
|
||||
* 3. I/O grids on the bottom side of FPGA only have ports on its top side
|
||||
* 4. I/O grids on the left side of FPGA only have ports on its right side
|
||||
*******************************************************************/
|
||||
static
|
||||
e_side find_grid_module_pin_side(t_type_ptr grid_type_descriptor,
|
||||
const e_side& border_side) {
|
||||
VTR_ASSERT(IO_TYPE == grid_type_descriptor);
|
||||
Side side_manager(border_side);
|
||||
return side_manager.get_opposite();
|
||||
}
|
||||
|
||||
/********************************************************************
|
||||
* Add ports/pins to a grid module
|
||||
* This function will iterate over all the pins that are defined
|
||||
|
|
@ -100,85 +86,6 @@ void add_grid_module_pb_type_ports(ModuleManager& module_manager,
|
|||
}
|
||||
}
|
||||
|
||||
/********************************************************************
|
||||
* Add module nets to connect a port of child pb_module
|
||||
* to the grid module
|
||||
*******************************************************************/
|
||||
static
|
||||
void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager,
|
||||
const ModuleId& grid_module,
|
||||
const ModuleId& child_module,
|
||||
const size_t& child_instance,
|
||||
t_type_ptr grid_type_descriptor,
|
||||
t_pb_graph_pin* pb_graph_pin,
|
||||
const e_side& border_side,
|
||||
const enum e_spice_pin2pin_interc_type& pin2pin_interc_type) {
|
||||
/* Find the pin side for I/O grids*/
|
||||
std::vector<e_side> grid_pin_sides;
|
||||
/* For I/O grids, we care only one side
|
||||
* Otherwise, we will iterate all the 4 sides
|
||||
*/
|
||||
if (IO_TYPE == grid_type_descriptor) {
|
||||
grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side));
|
||||
} else {
|
||||
grid_pin_sides.push_back(TOP);
|
||||
grid_pin_sides.push_back(RIGHT);
|
||||
grid_pin_sides.push_back(BOTTOM);
|
||||
grid_pin_sides.push_back(LEFT);
|
||||
}
|
||||
|
||||
/* num_pins/capacity = the number of pins that each type_descriptor has.
|
||||
* Capacity defines the number of type_descriptors in each grid
|
||||
* so the pin index at grid level = pin_index_in_type_descriptor
|
||||
* + type_descriptor_index_in_capacity * num_pins_per_type_descriptor
|
||||
*/
|
||||
size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster
|
||||
+ child_instance * grid_type_descriptor->num_pins / grid_type_descriptor->capacity;
|
||||
int pin_height = grid_type_descriptor->pin_height[grid_pin_index];
|
||||
for (const e_side& side : grid_pin_sides) {
|
||||
if (1 != grid_type_descriptor->pinloc[pin_height][side][grid_pin_index]) {
|
||||
continue;
|
||||
}
|
||||
/* Reach here, it means this pin is on this side */
|
||||
/* Create a net to connect the grid pin to child module pin */
|
||||
ModuleNetId net = module_manager.create_module_net(grid_module);
|
||||
/* Find the port in grid_module */
|
||||
vtr::Point<size_t> dummy_coordinate;
|
||||
std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_height, side, grid_pin_index, false);
|
||||
ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name);
|
||||
VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id));
|
||||
/* Grid port always has only 1 pin, it is assumed when adding these ports to the module
|
||||
* if you need a change, please also change the port adding codes
|
||||
*/
|
||||
size_t grid_module_pin_id = 0;
|
||||
/* Find the port in child module */
|
||||
std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port);
|
||||
ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name);
|
||||
VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id));
|
||||
size_t child_module_pin_id = pb_graph_pin->pin_number;
|
||||
/* Add net sources and sinks:
|
||||
* For input-to-input connection, net_source is grid pin, while net_sink is pb_graph_pin
|
||||
* For output-to-output connection, net_source is pb_graph_pin, while net_sink is grid pin
|
||||
*/
|
||||
switch (pin2pin_interc_type) {
|
||||
case INPUT2INPUT_INTERC:
|
||||
module_manager.add_module_net_source(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id);
|
||||
module_manager.add_module_net_sink(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id);
|
||||
break;
|
||||
case OUTPUT2OUTPUT_INTERC:
|
||||
module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id);
|
||||
module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id);
|
||||
break;
|
||||
default:
|
||||
vpr_printf(TIO_MESSAGE_ERROR,
|
||||
"(File:%s, [LINE%d]) Invalid pin-to-pin interconnection type!\n",
|
||||
__FILE__, __LINE__);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/********************************************************************
|
||||
* Add module nets to connect ports/pins of a grid module
|
||||
* to its child modules
|
||||
|
|
|
|||
Loading…
Reference in New Issue