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[Tool] Preconfigured testbench writer now supports icarus simulator

This commit is contained in:
tangxifan 2021-06-09 13:49:25 -06:00
parent f9404dc97d
commit 2299ce3157
2 changed files with 5 additions and 0 deletions
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2
openfpga/src/base/openfpga_verilog.cpp
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@ -223,6 +223,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path"); CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path"); CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_verbose = cmd.option("verbose"); CommandOptionId opt_verbose = cmd.option("verbose");
@ -233,6 +234,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir)); options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist)); options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark)); options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_preconfig_top_testbench(true); options.set_print_preconfig_top_testbench(true);

3
openfpga/src/base/openfpga_verilog_command.cpp
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@ -252,6 +252,9 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist"); CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
/* Add an option '--support_icarus_simulator' */
shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator");
/* Add an option '--explicit_port_mapping' */ /* Add an option '--explicit_port_mapping' */
shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists"); shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");