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Merge pull request #358 from lnis-uofu/ganesh_dev 

Testcase for benchmark specific variables
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tangxifan 2021-07-02 13:54:07 -06:00 committed by GitHub
parent f8fb056a42 edd5be2cae
commit 2214575a0a
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2 changed files with 9 additions and 4 deletions
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10
openfpga_flow/scripts/run_fpga_task.py
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@ -271,9 +271,11 @@ def generate_each_task_actions(taskname):
fallback=ys_rewrite_for_task_common) fallback=ys_rewrite_for_task_common)
CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width",
fallback=chan_width_common) fallback=chan_width_common)
benchVariable = []
for eachKey, eachValue in SynthSection.items(): for eachKey, eachValue in SynthSection.items():
eachKey = eachKey.replace(bech_name+"_","").upper() if bech_name in eachKey:
CurrBenchPara[eachKey] = eachValue eachKey = eachKey.replace(bech_name+"_", "").upper()
benchVariable = benchVariable+[f"--{eachKey}"] + [eachValue]
if GeneralSection.get("fpga_flow") == "vpr_blif": if GeneralSection.get("fpga_flow") == "vpr_blif":
# Check if activity file exist # Check if activity file exist
@ -335,7 +337,7 @@ def generate_each_task_actions(taskname):
"bench": bench, "bench": bench,
"name": "%02d_%s_%s" % (indx, bench["top_module"], lbl), "name": "%02d_%s_%s" % (indx, bench["top_module"], lbl),
"run_dir": flow_run_dir, "run_dir": flow_run_dir,
"commands": command, "commands": command + benchVariable,
"finished": False, "finished": False,
"status": False}) "status": False})
@ -346,6 +348,8 @@ def generate_each_task_actions(taskname):
# Make the directory name unique by including the benchmark index in the list. # Make the directory name unique by including the benchmark index in the list.
# This is because benchmarks may share the same top module names # This is because benchmarks may share the same top module names
def get_flow_rundir(arch, top_module, flow_params=None): def get_flow_rundir(arch, top_module, flow_params=None):
path = [ path = [
os.path.basename(arch).replace(".xml", ""), os.path.basename(arch).replace(".xml", ""),

3
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf
View File

@ -20,7 +20,6 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4Clk_cc_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4Clk_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_4clock_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_4clock_sim_openfpga.xml
openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml
openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml
@ -31,7 +30,9 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
bench0_top = counter4bit_2clock bench0_top = counter4bit_2clock
bench0_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml
bench1_top = and2_latch_2clock bench1_top = and2_latch_2clock
bench1_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test= end_flow_with_test=