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updated to line numbers of vpr8 example architecture

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Steve Corey 2018-07-10 13:02:21 -06:00
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jupyter_example.ipynb
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@ -232,41 +232,39 @@
"\n", "\n",
"## Layout and Routing\n", "## Layout and Routing\n",
"\n", "\n",
"Line 23 has the `<layout>` tag which specifies how the FPGA grid will be laid out. For this example: `<layout auto=\"1.000000\"/>` specifies an automatic grid with an aspect ratio of 1.0. A specific width and heigh could be specified instead of the automatic layout.\n", "Line 23 has the `<layout>` tag which specifies how the FPGA grid will be laid out. For this example: `<layout auto=\"1.000000\"/>` specifies an automatic grid with an aspect ratio of 1.0. A specific width and heigh could be specified instead of the automatic layout. Th rest of the `<layout>` section specifies that the perimeter will hav `io` blocks, the corners will be `EMPTY` and the rest of the FPGA will be filled with `clb` blocks. `io` and `clb` blocks are defined in the `<complexblocklist>` section.\n",
"\n", "\n",
"Line 24 begins the `<device>` tag which characterizes the components of the FPGA. `<sizing>` specifies the resistance of the minimum-width nmos and pmos transistors. `<area grid_logic_tile_area>` is used as an estimate of the size of one grid tile.\n", "Line 32 begins the `<device>` tag which characterizes the transistors and connections of the FPGA. `<sizing>` specifies the resistance of the minimum-width nmos and pmos transistors. `<area grid_logic_tile_area>` is used as an estimate of the size of one grid tile.\n",
"\n", "\n",
"Line 28 is the `<chan_width_distr>` section which sets the relative widths of the routing channels in various parts of the FPGA. Here, all channels are set to be distrubuted uniformly.\n", "Line 35 the `<chan_width_distr>` section sets the relative widths of the routing channels in various parts of the FPGA. Here, all channels are set to be distributed uniformly. Distribution options are `gaussian`, `pulse`, or `delta`.\n",
"\n", "\n",
"Line 33 is the `<switch_block>` tag which specifies the pattern of the switches used to connect the block routing segments. \n", "Line 42 is the `<switchlist>` section which specifies the switches used to connect wires and pins together. Resistance, in/out capacitance, delay through the switch, and component size.\n",
"\n", "\n",
"Line 35 is the `<switchlist>` section which specifies the switches used to connect wires and pins together. Resistance, in/out capacitance, delay through the switch, and component size.\n", "## redo segmentlist\n"
"\n",
"Line 38 begins the `<segmentlist>` section that specifies kinds of wire segments and their properties such as resistance and capacitance. `<sb type=\"pattern\">1 1</sb>` describes a pattern on a 1-length wire where there is a switch box between each grid element. `<cb type=\"pattern\">1</cb>` describes a pattern on a 1-length wire where there is a connection box at each grid element.\n"
] ]
}, },
{ {
"cell_type": "markdown", "cell_type": "markdown",
"metadata": {}, "metadata": {},
"source": [ "source": [
"Line 46 begins the `<complexblocklist>` section which is where the I/O and logic blocks are defined.\n", "Line 55 begins the `<complexblocklist>` section which is where the I/O and logic blocks are defined.\n",
"\n", "\n",
"# Skip I/O for now...\n", "# Skip I/O for now...\n",
"\n", "\n",
"\n", "\n",
"## Logic Blocks\n", "## Logic Blocks\n",
"\n", "\n",
"Line 106 is where the general purpuse *complex logic block* or *clb* definition begins. `<pb_type>` is the tag to define a physical block on the FPGA. Next, the inputs and outputs to the block are defined; here there are 10 inputs, 4 outputs, and 1 clock input. The inputs and outputs have `equivalent=true` attributes, which means that they are logically equivalent and so order doesn't matter when routing.\n", "Line 115 is where the general purpuse *complex logic block* or *clb* definition begins. `<pb_type>` is the tag to define a physical block on the FPGA. Next, the inputs and outputs to the block are defined; here there are 10 inputs, 4 outputs, and 1 clock input. The inputs and outputs have `equivalent=true` attributes, which means that they are logically equivalent and so order doesn't matter when routing.\n",
"\n", "\n",
"Line 112 defines the *basic logic element* or *BLE* that makes up the clb. The `<pb_type name=\"fle\" num_pb=\"4\">` attribute indicates that 4 of these BLEs called `fle` are contained in the surrounding `clb`. The next lines define 4 inputs, one output, and one clock line.\n", "Line 121 defines the *basic logic element* or *BLE* that makes up the clb. The `<pb_type name=\"fle\" num_pb=\"4\">` attribute indicates that 4 of these BLEs called `fle` are contained in the surrounding `clb`. The next lines define 4 inputs, one output, and one clock line.\n",
"\n", "\n",
"Skipping down to line 125, the core lookup-table of the BLE is defined: `<pb_type name=\"lut4\" blif_model=\".names\" num_pb=\"1\" class=\"lut\">`. This indicates 1 lookup-table named `lut4`; `.names` is the BLIF keyword for lookup-table. The next two lines show 4 inputs and 1 output to the LUT. The `<delay_matrix>` attribute specifies the propogation delay through the LUT's inputs to output.\n", "Skipping down to line 134, the core lookup-table of the BLE is defined: `<pb_type name=\"lut4\" blif_model=\".names\" num_pb=\"1\" class=\"lut\">`. This indicates 1 lookup-table named `lut4`; `.names` is the BLIF keyword for lookup-table. The next two lines show 4 inputs and 1 output to the LUT. The `<delay_matrix>` attribute specifies the propogation delay through the LUT's inputs to output.\n",
"\n", "\n",
"Line 138 defines the flip-flop in the BLE: `<pb_type name=\"ff\" blif_model=\".latch\" num_pb=\"1\" class=\"flipflop\">`: 1 flip-flop named `ff`; `.latch` is the BLIF keyword for flip-flop. The next lines specify the I/Os and timing parameters.\n", "Line 147 defines the flip-flop in the BLE: `<pb_type name=\"ff\" blif_model=\".latch\" num_pb=\"1\" class=\"flipflop\">`: 1 flip-flop named `ff`; `.latch` is the BLIF keyword for flip-flop. The next lines specify the I/Os and timing parameters.\n",
"\n", "\n",
"Skipping back up to line 117, a mode named `n1_lut4` for the block named `fle` is defined. A block can have multiple modes specified, but a block can only use one mode at a time. This particular block only defines one mode. The mode defines a block on line 199 named `ble4` which contains the LUT `lut4` and flip-flop `ff`.\n", "Skipping back up to line 126, a mode named `n1_lut4` for the block named `fle` is defined. A block can have multiple modes specified, but a block can only use one mode at a time. This particular block only defines one mode. The mode defines a block on line 128 named `ble4` which contains the LUT `lut4` and flip-flop `ff`.\n",
"\n", "\n",
"Moving back down to line 146, `<interconnect>` indicates how the blocks are connected. The `<direct>` element means to simply wire the nets together. Line 147 wires the input of `ble4` to the input of `lut4`, line 148 wires the output of `lut4` to the D-input of `ff`. Line 152 wires the clk inputs together. Line 153 defines a mux to set the output of `ble4` to be either the direct output of `lut4` or the latched output of `ff`." "Moving back down to line 155, `<interconnect>` indicates how the blocks are connected. The `<direct>` element means to simply wire the nets together. Line 156 wires the input of `ble4` to the input of `lut4`, line 157 wires the output of `lut4` to the D-input of `ff`. Line 161 wires the clk inputs together. Line 162 defines a mux to set the output of `ble4` to be either the direct output of `lut4` or the latched output of `ff`."
] ]
}, },
{ {