diff --git a/jupyter_example.ipynb b/jupyter_example.ipynb index 3848e0ba3..b2af46a91 100644 --- a/jupyter_example.ipynb +++ b/jupyter_example.ipynb @@ -232,41 +232,39 @@ "\n", "## Layout and Routing\n", "\n", - "Line 23 has the `` tag which specifies how the FPGA grid will be laid out. For this example: `` specifies an automatic grid with an aspect ratio of 1.0. A specific width and heigh could be specified instead of the automatic layout.\n", + "Line 23 has the `` tag which specifies how the FPGA grid will be laid out. For this example: `` specifies an automatic grid with an aspect ratio of 1.0. A specific width and heigh could be specified instead of the automatic layout. Th rest of the `` section specifies that the perimeter will hav `io` blocks, the corners will be `EMPTY` and the rest of the FPGA will be filled with `clb` blocks. `io` and `clb` blocks are defined in the `` section.\n", "\n", - "Line 24 begins the `` tag which characterizes the components of the FPGA. `` specifies the resistance of the minimum-width nmos and pmos transistors. `` is used as an estimate of the size of one grid tile.\n", + "Line 32 begins the `` tag which characterizes the transistors and connections of the FPGA. `` specifies the resistance of the minimum-width nmos and pmos transistors. `` is used as an estimate of the size of one grid tile.\n", "\n", - "Line 28 is the `` section which sets the relative widths of the routing channels in various parts of the FPGA. Here, all channels are set to be distrubuted uniformly.\n", + "Line 35 the `` section sets the relative widths of the routing channels in various parts of the FPGA. Here, all channels are set to be distributed uniformly. Distribution options are `gaussian`, `pulse`, or `delta`.\n", "\n", - "Line 33 is the `` tag which specifies the pattern of the switches used to connect the block routing segments. \n", + "Line 42 is the `` section which specifies the switches used to connect wires and pins together. Resistance, in/out capacitance, delay through the switch, and component size.\n", "\n", - "Line 35 is the `` section which specifies the switches used to connect wires and pins together. Resistance, in/out capacitance, delay through the switch, and component size.\n", - "\n", - "Line 38 begins the `` section that specifies kinds of wire segments and their properties such as resistance and capacitance. `1 1` describes a pattern on a 1-length wire where there is a switch box between each grid element. `1` describes a pattern on a 1-length wire where there is a connection box at each grid element.\n" + "## redo segmentlist\n" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ - "Line 46 begins the `` section which is where the I/O and logic blocks are defined.\n", + "Line 55 begins the `` section which is where the I/O and logic blocks are defined.\n", "\n", "# Skip I/O for now...\n", "\n", "\n", "## Logic Blocks\n", "\n", - "Line 106 is where the general purpuse *complex logic block* or *clb* definition begins. `` is the tag to define a physical block on the FPGA. Next, the inputs and outputs to the block are defined; here there are 10 inputs, 4 outputs, and 1 clock input. The inputs and outputs have `equivalent=true` attributes, which means that they are logically equivalent and so order doesn't matter when routing.\n", + "Line 115 is where the general purpuse *complex logic block* or *clb* definition begins. `` is the tag to define a physical block on the FPGA. Next, the inputs and outputs to the block are defined; here there are 10 inputs, 4 outputs, and 1 clock input. The inputs and outputs have `equivalent=true` attributes, which means that they are logically equivalent and so order doesn't matter when routing.\n", "\n", - "Line 112 defines the *basic logic element* or *BLE* that makes up the clb. The `` attribute indicates that 4 of these BLEs called `fle` are contained in the surrounding `clb`. The next lines define 4 inputs, one output, and one clock line.\n", + "Line 121 defines the *basic logic element* or *BLE* that makes up the clb. The `` attribute indicates that 4 of these BLEs called `fle` are contained in the surrounding `clb`. The next lines define 4 inputs, one output, and one clock line.\n", "\n", - "Skipping down to line 125, the core lookup-table of the BLE is defined: ``. This indicates 1 lookup-table named `lut4`; `.names` is the BLIF keyword for lookup-table. The next two lines show 4 inputs and 1 output to the LUT. The `` attribute specifies the propogation delay through the LUT's inputs to output.\n", + "Skipping down to line 134, the core lookup-table of the BLE is defined: ``. This indicates 1 lookup-table named `lut4`; `.names` is the BLIF keyword for lookup-table. The next two lines show 4 inputs and 1 output to the LUT. The `` attribute specifies the propogation delay through the LUT's inputs to output.\n", "\n", - "Line 138 defines the flip-flop in the BLE: ``: 1 flip-flop named `ff`; `.latch` is the BLIF keyword for flip-flop. The next lines specify the I/Os and timing parameters.\n", + "Line 147 defines the flip-flop in the BLE: ``: 1 flip-flop named `ff`; `.latch` is the BLIF keyword for flip-flop. The next lines specify the I/Os and timing parameters.\n", "\n", - "Skipping back up to line 117, a mode named `n1_lut4` for the block named `fle` is defined. A block can have multiple modes specified, but a block can only use one mode at a time. This particular block only defines one mode. The mode defines a block on line 199 named `ble4` which contains the LUT `lut4` and flip-flop `ff`.\n", + "Skipping back up to line 126, a mode named `n1_lut4` for the block named `fle` is defined. A block can have multiple modes specified, but a block can only use one mode at a time. This particular block only defines one mode. The mode defines a block on line 128 named `ble4` which contains the LUT `lut4` and flip-flop `ff`.\n", "\n", - "Moving back down to line 146, `` indicates how the blocks are connected. The `` element means to simply wire the nets together. Line 147 wires the input of `ble4` to the input of `lut4`, line 148 wires the output of `lut4` to the D-input of `ff`. Line 152 wires the clk inputs together. Line 153 defines a mux to set the output of `ble4` to be either the direct output of `lut4` or the latched output of `ff`." + "Moving back down to line 155, `` indicates how the blocks are connected. The `` element means to simply wire the nets together. Line 156 wires the input of `ble4` to the input of `lut4`, line 157 wires the output of `lut4` to the D-input of `ff`. Line 161 wires the clk inputs together. Line 162 defines a mux to set the output of `ble4` to be either the direct output of `lut4` or the latched output of `ff`." ] }, {