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[Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option

This commit is contained in:
tangxifan 2021-06-24 16:56:28 -06:00
parent c1dab21686
commit 21d1519658
4 changed files with 10 additions and 16 deletions
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6
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
View File

@ -206,12 +206,6 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
/* Print the title */
print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features"));
/* To enable signal initialization */
if (true == verilog_testbench_opts.include_signal_init()) {
print_verilog_define_flag(fp, std::string(VERILOG_SIGNAL_INIT_PREPROC_FLAG), 1);
fp << std::endl;
}
/* To enable functional verfication with Icarus */
if (true == verilog_testbench_opts.support_icarus_simulator()) {
print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1);

1
openfpga/src/fpga_verilog/verilog_constants.h
View File

@ -7,7 +7,6 @@ constexpr char* VERILOG_NETLIST_FILE_POSTFIX = ".v";
constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns
constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation
constexpr char* VERILOG_SIGNAL_INIT_PREPROC_FLAG = "ENABLE_SIGNAL_INITIALIZATION"; // the flag to enable signal initialization during compilation
constexpr char* VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation
constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to enable initial functional verification
constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification

6
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -507,12 +507,16 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
circuit_lib, sram_model,
bitstream_manager);
/* Add signal initialization */
/* Add signal initialization:
* Bypass writing codes to files due to the autogenerated codes are very large.
*/
if (true == options.include_signal_init()) {
print_verilog_testbench_signal_initialization(fp,
std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME),
circuit_lib,
module_manager,
top_module);
}
/* Testbench ends*/
print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX));

3
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -911,7 +911,6 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp,
/* Add signal initialization Verilog codes */
fp << std::endl;
fp << "`ifdef " << VERILOG_SIGNAL_INIT_PREPROC_FLAG << std::endl;
for (const CircuitModelId& signal_init_circuit_model : signal_init_circuit_models) {
/* Find the module id corresponding to the circuit model from module graph */
ModuleId primitive_module = module_manager.find_module(circuit_lib.model_name(signal_init_circuit_model));
@ -924,8 +923,6 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp,
module_manager, top_module,
primitive_module);
}
fp << "`endif" << std::endl;
}
} /* end namespace openfpga */