diff --git a/.travis/regression.sh b/.travis/regression.sh
index 1b9774db3..9ec6dbee1 100755
--- a/.travis/regression.sh
+++ b/.travis/regression.sh
@@ -9,6 +9,13 @@ tb_formal_postfix="_top_formal_verification_random_tb"
verilog_output_dirname="${benchmark}_Verilog"
log_file="${benchmark}_sim.log"
+cd fpga_flow/scripts
+
+perl rewrite_path_in_file.pl -i ../arch/template/k6_N10_sram_chain_HC_template.xml
+perl rewrite_path_in_file.pl -i ../../vpr7_x2p/vpr/regression_verilog.sh
+
+cd -
+
# Move to vpr folder
cd vpr7_x2p/vpr
@@ -17,7 +24,7 @@ rm -f $log_file
rm -f $compiled_file
# Start the script -> run the fpga generation -> run the simulation -> check the log file
-source .regression_verilog.sh
+source regression_verilog.sh
iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
vvp $compiled_file -j 16 >> $log_file
diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
new file mode 100644
index 000000000..b7630261f
--- /dev/null
+++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
@@ -0,0 +1,1040 @@
+
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+
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+ 10e-12
+
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+ 10e-12
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+
+ 10e-12
+
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
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+ 10e-12
+
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+
+
+ 10e-12 5e-12 5e-12
+
+
+ 10e-12 5e-12 5e-12
+
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+
+
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+
+
+ 10e-12 10e-12
+
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+ 10e-12 10e-12
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+ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+
+
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+ 1 1 1 1 1
+ 1 1 1 1
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+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
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+ 255e-12
+ 255e-12
+ 255e-12
+ 255e-12
+ 255e-12
+
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+ 202e-12
+ 202e-12
+ 202e-12
+ 202e-12
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+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+
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+
+
+ clb.cin clb.cin_trick clb.regin clb.clk
+ clb.I0[9:0] clb.I1[9:0] clb.O[9:0]
+ clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10]
+
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diff --git a/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.act b/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.act
new file mode 100644
index 000000000..a58956a8e
--- /dev/null
+++ b/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.act
@@ -0,0 +1,67 @@
+cint01 0.485400 0.188600
+n01 0.489000 0.213200
+cint02 0.502400 0.203200
+n02 0.509200 0.195200
+cint03 0.507200 0.192200
+n03 0.502400 0.201600
+cint04 0.463200 0.199400
+n04 0.522000 0.191000
+n05 0.486800 0.204800
+reg0 0.463000 0.195400
+reg1 0.487400 0.196600
+reg2 0.506200 0.195000
+reg3 0.492200 0.208200
+reg4 0.507200 0.204800
+reg5 0.500400 0.200600
+reg6 0.500800 0.203400
+reg7 0.509600 0.198800
+reg8 0.492200 0.188000
+reg9 0.504800 0.204400
+reg10 0.507600 0.203200
+reg11 0.494200 0.203600
+clk 0.534600 0.203800
+a_0 0.478200 0.203800
+a_1 0.514800 0.208600
+a_2 0.505800 0.204600
+a_3 0.500000 0.195200
+b_0 0.530800 0.192800
+b_1 0.495800 0.195400
+b_2 0.496600 0.201200
+b_3 0.492000 0.200200
+cin 0.502600 0.202200
+e 0.495200 0.201000
+f 0.504000 0.203400
+g 0.498200 0.202000
+reg_a_0 0.478200 0.203800
+reg_a_1 0.514800 0.208600
+reg_a_2 0.505800 0.204600
+reg_a_3 0.500000 0.195200
+reg_b_0 0.530800 0.192800
+reg_b_1 0.495800 0.195400
+reg_b_2 0.496600 0.201200
+reg_b_3 0.492000 0.200200
+reg_cin 0.502600 0.202200
+sum_0 0.489000 0.213200
+sum_1 0.509200 0.195200
+sum_2 0.502400 0.201600
+sum_3 0.522000 0.191000
+cout 0.486800 0.204800
+ref0 0.000000 0.000000
+n57 0.478200 0.097457
+n62 0.514800 0.107387
+n67 0.505800 0.103487
+n72 0.500000 0.097600
+n77 0.530800 0.102338
+n82 0.495800 0.096879
+n87 0.496600 0.099916
+n92 0.492000 0.098498
+n97 0.502600 0.101626
+d0 0.617800 0.046719
+x 0.492200 0.102476
+y 0.509600 0.101308
+z 0.494200 0.100619
+n102 0.489000 0.104255
+n106 0.509200 0.099396
+n110 0.502400 0.101284
+n114 0.522000 0.099702
+n118 0.486800 0.099697
diff --git a/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif b/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif
new file mode 100644
index 000000000..d63bca69d
--- /dev/null
+++ b/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif
@@ -0,0 +1,93 @@
+# Benchmark "test" written by ABC on Tue Apr 30 17:17:10 2019
+.model test_modes
+.inputs clk a_0 a_1 a_2 a_3 b_0 b_1 b_2 b_3 cin e f g
+.outputs sum_0 sum_1 sum_2 sum_3 cout x y z
+
+.latch n57 reg_a_0 re clk 0
+.latch n62 reg_a_1 re clk 0
+.latch n67 reg_a_2 re clk 0
+.latch n72 reg_a_3 re clk 0
+.latch n77 reg_b_0 re clk 0
+.latch n82 reg_b_1 re clk 0
+.latch n87 reg_b_2 re clk 0
+.latch n92 reg_b_3 re clk 0
+.latch n97 reg_cin re clk 0
+.latch n102 sum_0 re clk 0
+.latch n106 sum_1 re clk 0
+.latch n110 sum_2 re clk 0
+.latch n114 sum_3 re clk 0
+.latch n118 cout re clk 0
+
+
+.subckt adder a=reg_a_0 b=reg_b_0 cin=reg_cin cout=cint01 sumout=n01
+.subckt adder a=reg_a_1 b=reg_b_1 cin=cint01 cout=cint02 sumout=n02
+.subckt adder a=reg_a_2 b=reg_b_2 cin=cint02 cout=cint03 sumout=n03
+.subckt adder a=reg_a_3 b=reg_b_3 cin=cint03 cout=cint04 sumout=n04
+.subckt adder a=ref0 b=ref0 cin=cint04 cout=unconn sumout=n05
+.subckt shift D=d0 clk=clk Q=reg0
+.subckt shift D=reg0 clk=clk Q=reg1
+.subckt shift D=reg1 clk=clk Q=reg2
+.subckt shift D=reg2 clk=clk Q=reg3
+.subckt shift D=reg3 clk=clk Q=reg4
+.subckt shift D=reg4 clk=clk Q=reg5
+.subckt shift D=reg5 clk=clk Q=reg6
+.subckt shift D=reg6 clk=clk Q=reg7
+.subckt shift D=reg7 clk=clk Q=reg8
+.subckt shift D=reg8 clk=clk Q=reg9
+.subckt shift D=reg9 clk=clk Q=reg10
+.subckt shift D=reg10 clk=clk Q=reg11
+
+.names ref0
+ 0
+.names a_0 n57
+1 1
+.names a_1 n62
+1 1
+.names a_2 n67
+1 1
+.names a_3 n72
+1 1
+.names b_0 n77
+1 1
+.names b_1 n82
+1 1
+.names b_2 n87
+1 1
+.names b_3 n92
+1 1
+.names cin n97
+1 1
+.names e f g d0
+1-1 1
+-0- 1
+.names reg3 x
+1 1
+.names reg7 y
+1 1
+.names reg11 z
+1 1
+.names n01 n102
+1 1
+.names n02 n106
+1 1
+.names n03 n110
+1 1
+.names n04 n114
+1 1
+.names n05 n118
+1 1
+.end
+
+
+.model adder
+.inputs a b cin
+.outputs cout sumout
+.blackbox
+.end
+
+
+.model shift
+.inputs D clk
+.outputs Q
+.blackbox
+.end
diff --git a/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.power b/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.power
new file mode 100644
index 000000000..1d53436ae
--- /dev/null
+++ b/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.power
@@ -0,0 +1,172 @@
+----------------------------------- Summary ------------------------------------
+Circuit: /research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/fpga_flow/benchmarks/Blif/Test_Modes/test_modes
+Architecture: k6_N10_sram_chain_HC_template.xml
+Technology (nm): 45
+Voltage: 0.90
+Temperature: 85
+Critical Path: 5.8141e-09
+Size of FPGA: 2 x 2
+Channel Width: 200
+
+----------------------------------- Warnings -----------------------------------
+No transistor counter function for BLIF model: .frac_lut6
+No transistor counter function for BLIF model: .subckt adder
+No transistor counter function for BLIF model: .subckt shift
+Attempted to search for a transistor with a capacitance smaller than the smallest in the technology file.
+
+No dynamic power defined for BLIF model: .subckt adder
+No leakage power defined for BLIF model: .subckt adder
+No dynamic power defined for BLIF model: .frac_lut6
+No leakage power defined for BLIF model: .frac_lut6
+No dynamic power defined for BLIF model: .subckt shift
+No leakage power defined for BLIF model: .subckt shift
+
+------------------------------- Power Breakdown --------------------------------
+Component Power (W) %-Total %-Dynamic Method
+
+Total 0.0002701 1 0.7897
+ Routing 0.0001289 0.4773 0.7668
+ Switch Box 2.212e-05 0.08191 0
+ Connection Box 0.0001068 0.3954 0.9256
+ Global Wires 0 0 -nan
+ PB Types 8.066e-05 0.2986 0.6884
+ Primitives 4.913e-05 0.1819 0.8837
+ Interc Structures 8.866e-06 0.03283 0.5489
+ Buffers and Wires 2.266e-05 0.08389 0.3197
+ Other Estimation Methods 0 0 -nan
+ Clock 6.051e-05 0.224 0.9736
+
+---------------------------- Power Breakdown by PB -----------------------------
+This sections provides a detailed breakdown of power usage by PB (physical
+block). For each PB, the power is listed, which is the sum power of all
+instances of the block. It also indicates its percentage of total power (entire
+FPGA), as well as the percentage of its power that is dynamic (vs. static). It
+also indicates the method used for power estimation.
+
+The data includes:
+ Modes: When a pb contains multiple modes, each mode is listed, with
+ its power statistics.
+ Bufs/Wires: Power of all local buffers and local wire switching
+ (transistor-level estimation only).
+ Interc: Power of local interconnect multiplexers (transistor-
+ level estimation only)
+
+Description of Estimation Methods:
+ Transistor Auto-Size: Transistor-level power estimation. Local buffers and
+ wire lengths are automatically sized. This is the default estimation
+ method.
+ Transistor Specify-Size: Transistor-level power estimation. Local buffers
+ and wire lengths are only inserted where specified by the user in the
+ architecture file.
+ Pin-Toggle: Dynamic power is calculated using enery-per-toggle of the PB
+ input pins. Static power is absolute.
+ C-Internal: Dynamic power is calculated using an internal equivalent
+ capacitance for PB type. Static power is absolute.
+ Absolute: Dynamic and static power are absolutes from the architecture file.
+ Sum of Children: Power of PB is only the sum of all child PBs; interconnect
+ between the PB and its children is ignored.
+ Ignore: Power of PB is ignored.
+
+
+Component Power (W) %-Total %-Dynamic Method
+
+io 0 0 -nan Ignore
+clb 8.066e-05 0.2986 0.6884 Transistor Auto-Size
+ Bufs/Wires 1.43e-05 0.05294 0.2804
+ Interc: 8.462e-06 0.03133 0.542
+ crossbar0 3.015e-06 0.01116 0.5188
+ crossbar1 3.264e-06 0.01208 0.5568
+ crossbar2 1.076e-06 0.003984 0.5484
+ crossbar3 8.245e-07 0.003053 0.5364
+ crossbar4 0 0 -nan
+ crossbar5 0 0 -nan
+ clks 0 0 -nan
+ carry_in 2.821e-07 0.001045 0.6112
+ fle 5.79e-05 0.2144 0.8106 Transistor Auto-Size
+ Bufs/Wires 6.769e-06 0.02506 0.3446
+ Mode:fle_phy 3.361e-05 0.1244 0.9139
+ Interc: 0 0 -nan
+ direct_clk 0 0 -nan
+ mux1 0 0 -nan
+ mux2 0 0 -nan
+ frac_logic 3.388e-07 0.001254 0 Transistor Auto-Size
+ Bufs/Wires 3.388e-07 0.001254 0
+ Interc: 0 0 -nan
+ mux1 0 0 -nan
+ mux2 0 0 -nan
+ frac_lut6 0 0 -nan Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ adder_phy 0 0 -nan Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ ff_phy 3.327e-05 0.1232 0.9232 Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ Mode:n2_lut5 1.741e-05 0.06444 0.7925
+ Interc: 0 0 -nan
+ lut5inter 1.741e-05 0.06444 0.7925 Transistor Auto-Size
+ Bufs/Wires 5.658e-07 0.002095 0.6977
+ Interc: 0 0 -nan
+ complete1 0 0 -nan
+ ble5 1.684e-05 0.06235 0.7956 Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ Mode:blut5 1.12e-05 0.04146 0.8091
+ Interc: 0 0 -nan
+ flut5 1.12e-05 0.04146 0.8091 Transistor Auto-Size
+ Bufs/Wires 2.007e-07 0.000743 0.7628
+ Interc: 2.646e-07 0.0009797 0.684
+ mux1 2.646e-07 0.0009797 0.684
+ lut5 1.655e-06 0.006127 0.2417 Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ Mode:wire 0 0 -nan
+ Interc: 0 0 -nan
+ complete:lut5 0 0 -nan
+ Mode:lut5 1.655e-06 0.006127 0.2417
+ Interc: 0 0 -nan
+ lut 1.655e-06 0.006127 0.2417 Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ ff 9.079e-06 0.03361 0.9173 Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ Mode:arithmetic 5.641e-06 0.02088 0.7689
+ Interc: 0 0 -nan
+ arithmetic 5.641e-06 0.02088 0.7689 Transistor Auto-Size
+ Bufs/Wires 3.732e-07 0.001382 0.7081
+ Interc: 1.399e-07 0.0005179 0.708
+ sumout 1.399e-07 0.0005179 0.708
+ lut4 7.913e-07 0.00293 0 Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ Mode:wire 0 0 -nan
+ Interc: 0 0 -nan
+ complete:lut4 0 0 -nan
+ Mode:lut4 7.913e-07 0.00293 0
+ Interc: 0 0 -nan
+ lut 7.913e-07 0.00293 0 Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ adder 0 0 -nan Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ ff 4.336e-06 0.01606 0.9163 Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ Mode:n1_lut6 0 0 -nan
+ Interc: 0 0 -nan
+ ble6 0 0 -nan Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ Interc: 0 0 -nan
+ mux1 0 0 -nan
+ lut6 0 0 -nan Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ Mode:wire 0 0 -nan
+ Interc: 0 0 -nan
+ complete:lut6 0 0 -nan
+ Mode:lut6 0 0 -nan
+ Interc: 0 0 -nan
+ lut 0 0 -nan Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ ff 0 0 -nan Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+ Mode:shift_register 1.134e-07 0.0004199 0.7826
+ Interc: 0 0 -nan
+ ble_shift 1.134e-07 0.0004199 0.7826 Transistor Auto-Size
+ Bufs/Wires 1.134e-07 0.0004199 0.7826
+ Interc: 0 0 -nan
+ direct3 0 0 -nan
+ ff 0 0 -nan Transistor Auto-Size
+ Bufs/Wires 0 0 -nan
+
diff --git a/fpga_flow/benchmarks/Verilog/Test_Modes/test_modes.v b/fpga_flow/benchmarks/Verilog/Test_Modes/test_modes.v
new file mode 100644
index 000000000..8090d2903
--- /dev/null
+++ b/fpga_flow/benchmarks/Verilog/Test_Modes/test_modes.v
@@ -0,0 +1,78 @@
+////////////////////////////////////////////////////////
+// //
+// Benchmark using all modes of k8 architecture //
+// //
+////////////////////////////////////////////////////////
+
+`timescale 1 ns/ 1 ps
+
+module test_modes(
+ clk,
+ a_0,
+ a_1,
+ a_2,
+ a_3,
+ b_0,
+ b_1,
+ b_2,
+ b_3,
+ cin,
+ e,
+ f,
+ g,
+ sum_0,
+ sum_1,
+ sum_2,
+ sum_3,
+ cout,
+ x,
+ y,
+ z );
+
+ input wire clk, a_0, a_1, a_2, a_3, b_0, b_1, b_2, b_3, cin, e, f, g;
+ output reg sum_0, sum_1, sum_2, sum_3, cout;
+ output wire x, y, z;
+
+ wire d0;
+ wire [4:0] n0;
+ wire [3:0] a, b;
+ reg reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg_a_0, reg_a_1, reg_a_2, reg_a_3, reg_b_0, reg_b_1, reg_b_2, reg_b_3, reg_cin;
+
+ assign a = {reg_a_3, reg_a_2, reg_a_1, reg_a_0};
+ assign b = {reg_b_3, reg_b_2, reg_b_1, reg_b_0};
+ assign d0 = (e && g) || !f;
+ assign n0 = a + b + reg_cin;
+ assign x = reg3;
+ assign y = reg7;
+ assign z = reg11;
+
+ always @(posedge clk) begin
+ reg0 <= d0;
+ reg1 <= reg0;
+ reg2 <= reg1;
+ reg3 <= reg2;
+ reg4 <= reg3;
+ reg5 <= reg4;
+ reg6 <= reg5;
+ reg7 <= reg6;
+ reg8 <= reg7;
+ reg9 <= reg8;
+ reg10 <= reg9;
+ reg11 <= reg10;
+ reg_a_0 <= a_0;
+ reg_a_1 <= a_1;
+ reg_a_2 <= a_2;
+ reg_a_3 <= a_3;
+ reg_b_0 <= b_0;
+ reg_b_1 <= b_1;
+ reg_b_2 <= b_2;
+ reg_b_3 <= b_3;
+ reg_cin <= cin;
+ sum_0 <= n0[0];
+ sum_1 <= n0[1];
+ sum_2 <= n0[2];
+ sum_3 <= n0[3];
+ cout <= n0[4];
+ end
+
+endmodule
diff --git a/fpga_flow/configs/regression/k6_N10_regression_TT.conf b/fpga_flow/configs/regression/k6_N10_regression_TT.conf
deleted file mode 100644
index d714d85c4..000000000
--- a/fpga_flow/configs/regression/k6_N10_regression_TT.conf
+++ /dev/null
@@ -1,31 +0,0 @@
-# Standard Configuration Example
-[dir_path]
-script_base = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/scripts/
-benchmark_dir = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC
-yosys_path = /home/travis/build/LNIS-Projects/OpenFPGA/yosys/yosys
-odin2_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/odin2.exe
-cirkit_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/cirkit
-abc_path = /home/travis/build/LNIS-Projects/OpenFPGA/yosys/yosys-abc
-abc_mccl_path = /home/travis/build/LNIS-Projects/OpenFPGA/abc_with_bb_support/abc
-abc_with_bb_support_path = /home/travis/build/LNIS-Projects/OpenFPGA/abc_with_bb_support/abc
-mpack1_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/mpack1
-m2net_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/m2net
-mpack2_path = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/not_used_atm/mpack2
-vpr_path = /home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/vpr
-rpt_dir = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/results
-ace_path = /home/travis/build/LNIS-Projects/OpenFPGA/ace2/ace
-
-[flow_conf]
-flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
-vpr_arch = /home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/ARCH/.travis_k6_N10_sram_chain_HC.xml # temporary path to the architecture
-#vpr_arch = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/arch/fpga_spice/.travis_k6_N10_sram_chain_HC.xml # Path when Architecture will move
-mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
-m2net_conf = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
-mpack2_arch = K6_pattern7_I24.arch
-power_tech_xml = /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
-
-[csv_tags]
-mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
-mpack2_tags = BLE Number:|BLE Fill Rate:
-vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:
-vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff
diff --git a/fpga_flow/regression_fpga_flow.sh b/fpga_flow/regression_fpga_flow.sh
index 971fe0d0b..c0968d9be 100755
--- a/fpga_flow/regression_fpga_flow.sh
+++ b/fpga_flow/regression_fpga_flow.sh
@@ -3,18 +3,20 @@
set -e
# Make sure a clear start
pwd_path="$PWD"
-task_name="k6_N10_regression_TT"
+task_name="k6_N10_regression_0"
config_file="$PWD/configs/regression/${task_name}.conf"
-bench_txt="$PWD/benchmarks/List/mcnc_benchmark.txt"
+bench_txt="$PWD/benchmarks/List/test_modes.txt"
rpt_file="$PWD/csv_rpts/fpga_spice/${task_name}.csv"
task_file="$PWD/vpr_fpga_spice_task_lists/${task_name}"
verilog_path="${PWD}/regression_MCNC"
# FPGA-SPICE
-rm -rf ${pwd_path}/results
+rm -rf ${pwd_path}/results_regression
cd ${pwd_path}/scripts
+perl rewrite_path_in_file.pl -i $config_file
+
# SRAM FPGA
# TT case
perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -remove_designs -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -end_flow_with_test -power
diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl
index ba0b96750..5291b508a 100644
--- a/fpga_flow/scripts/fpga_flow.pl
+++ b/fpga_flow/scripts/fpga_flow.pl
@@ -1433,24 +1433,24 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
print "./$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $packer_opts $chan_width_opt $vpr_spice_opts $other_opt > $log\n";
system("./$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $packer_opts $chan_width_opt $vpr_spice_opts $other_opt > $log");
- open(F, $log);
- my @lines=;
- close F;
- my @results = grep(" ", @lines);
- if($#results >= 1){
- foreach my $line (0..$#results){
- print "$results[$line]\n";
- }
- }
- if ("on" eq $opt_ptr->{vpr_fpga_verilog_dir}) {
- opendir my($dh), $opt_ptr->{vpr_fpga_verilog_dir_val} or die "\nFolder not created!!\n\n";
- my @files = readdir $dh;
- closedir $dh;
- foreach my $file (0..$#files){
- print "$files[$file]\t";
- }
- print "\n";
- }
+ #open(F, $log);
+ #my @lines=;
+ #close F;
+ #my @results = grep(" ", @lines);
+ #if($#results >= 1){
+ # foreach my $line (0..$#results){
+ # print "$results[$line]\n";
+ # }
+ #}
+ #if ("on" eq $opt_ptr->{vpr_fpga_verilog_dir}) {
+ # opendir my($dh), $opt_ptr->{vpr_fpga_verilog_dir_val} or die "\nFolder not created!!\n\n";
+ # my @files = readdir $dh;
+ # closedir $dh;
+ # foreach my $file (0..$#files){
+ # print "$files[$file]\t";
+ # }
+ 3 print "\n";
+ #}
chdir $cwd;
}
@@ -1866,6 +1866,9 @@ sub run_yosys_vpr_flow($ $ $ $ $)
$rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag";
&generate_path($rpt_dir);
+ # Adapt paths on architecture file
+ `perl rewrite_path_in_file.pl -i $vpr_arch`;
+
# Run Yosys flow
$yosys_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark_file";
$prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_";
diff --git a/fpga_flow/scripts/rewrite_path_in_file.pl b/fpga_flow/scripts/rewrite_path_in_file.pl
new file mode 100644
index 000000000..fadedb606
--- /dev/null
+++ b/fpga_flow/scripts/rewrite_path_in_file.pl
@@ -0,0 +1,108 @@
+#!usr/bin/perl -w
+use strict;
+use Cwd;
+#use Shell;
+use FileHandle;
+#Use the time
+use Time::gmtime;
+
+my $my_file;
+my $keyword = "OPENFPGAPATHKEYWORD";
+my $folder_top = "OpenFPGA";
+
+sub print_usage()
+{
+ print "Usage:\n";
+ print " perl [-options]\n";
+ print " Options:(Mandatory!)\n";
+ print " -i \n";
+ print "\n";
+ return;
+}
+
+sub opts_read()
+{
+ if ($#ARGV == -1){
+ print "Error: Not enough input argument!\n";
+ &print_usage();
+ exit(1);
+ } else {
+ for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++){
+ if ("-i" eq $ARGV[$iargv]){
+ $my_file = $ARGV[$iargv+1];
+ $iargv++;
+ } else {
+ die "WRONG ARGUMENT";
+ }
+ }
+ }
+ return;
+}
+
+sub rewriting_required_check($)
+{
+ my ($file) = @_;
+ open(F, $file);
+ my @lines=;
+ close F;
+ my $grep_result = grep ($keyword, @lines);
+ if($grep_result >= 1){
+ print "Rewrite needed\n";
+ return 1;
+ } else {
+ print "Rewrite NOT needed\n";
+ return 0;
+ }
+}
+
+sub save_original($)
+{
+ my ($template) = @_;
+ my $renamed_template = "$template".".bak";
+ rename($template, $renamed_template);
+
+ return $renamed_template;
+}
+
+sub findPath(){
+ my $path;
+ my $dir = cwd;
+ my @folders = split("/", $dir);
+ for(my $count = 0; $count < $#folders; $count++){
+ if($folders[$count] eq ""){
+ } else {
+ $path = "$path"."/"."$folders[$count]";
+ if($folders[$count] eq $folder_top){
+ print "$path\n";
+ return $path;
+ }
+ }
+ }
+ die "ERROR: Script launched from the outside of the $folder_top folder!\n";
+}
+
+sub create_new($ $)
+{
+ my ($file, $template) = @_;
+ my $myPath = &findPath();
+ open(IN, '<'.$template);
+ open(OUT, '>'.$file);
+ while(){
+ $_ =~ s/$keyword/$myPath/g;
+ print OUT $_;
+ }
+ return;
+}
+
+sub main()
+{
+ &opts_read();
+ my $rewrite_needed = &rewriting_required_check($my_file);
+ if($rewrite_needed == 1){
+ my $template_file = &save_original($my_file);
+ &create_new($my_file, $template_file);
+ }
+ return;
+}
+
+&main();
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c
index 8d1558e1d..304cb8c59 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c
@@ -585,7 +585,7 @@ int get_rr_node_index_in_cb_info(t_rr_node* cur_rr_node,
/* Determine the coordinate of a chan_rr_node in a SB_info
* Return chan_type & chan_rr_node_x & chan_rr_node_y
*/
-void get_chan_rr_node_coorindate_in_sb_info(t_sb cur_sb_info,
+void get_chan_rr_node_coordinate_in_sb_info(t_sb cur_sb_info,
int chan_rr_node_side,
t_rr_type* chan_type,
int* chan_rr_node_x, int* chan_rr_node_y) {
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.h
index 2c72cbfdb..511b18d34 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.h
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.h
@@ -41,7 +41,7 @@ void get_rr_node_side_and_index_in_sb_info(t_rr_node* cur_rr_node,
OUTP int* cur_rr_node_side,
OUTP int* cur_rr_node_index);
-void get_chan_rr_node_coorindate_in_sb_info(t_sb cur_sb_info,
+void get_chan_rr_node_coordinate_in_sb_info(t_sb cur_sb_info,
int chan_rr_node_side,
t_rr_type* chan_type,
int* chan_rr_node_x, int* chan_rr_node_y);
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c
index 1993a6ecd..e0d4457d6 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c
@@ -1274,6 +1274,7 @@ int add_virtual_sources_to_rr_graph_multi_sources(t_rr_graph* local_rr_graph) {
local_rr_graph->rr_node[unique_src_node].fan_in = 0;
local_rr_graph->rr_node[unique_src_node].num_drive_rr_nodes = 0;
local_rr_graph->rr_node[unique_src_node].drive_rr_nodes = NULL;
+ local_rr_graph->rr_node[unique_src_node].pb_graph_pin = NULL;
local_rr_graph->rr_node[unique_src_node].num_edges = local_rr_graph->net_num_sources[inet];
local_rr_graph->rr_node[unique_src_node].edges = (int*) my_calloc(local_rr_graph->rr_node[unique_src_node].num_edges, sizeof(int));
local_rr_graph->rr_node[unique_src_node].switches = (short*) my_calloc(local_rr_graph->rr_node[unique_src_node].num_edges, sizeof(short));
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c
index 4946a9e94..5fb871061 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c
@@ -274,7 +274,7 @@ void fprint_switch_box_chan_port(FILE* fp,
/* Make sure this node is included in this sb_info */
assert((-1 != index)&&(-1 != chan_side));
- get_chan_rr_node_coorindate_in_sb_info(cur_sb_info, chan_side,
+ get_chan_rr_node_coordinate_in_sb_info(cur_sb_info, chan_side,
&chan_rr_node_type, &chan_rr_node_x, &chan_rr_node_y);
assert(cur_rr_node->type == chan_rr_node_type);
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
index cd1ea0510..14da3f43d 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
@@ -645,7 +645,7 @@ void dump_verilog_switch_box_chan_port(FILE* fp,
/* Make sure this node is included in this sb_info */
assert((-1 != index)&&(-1 != chan_side));
- get_chan_rr_node_coorindate_in_sb_info((*cur_sb_info), chan_side,
+ get_chan_rr_node_coordinate_in_sb_info((*cur_sb_info), chan_side,
&chan_rr_node_type, &chan_rr_node_x, &chan_rr_node_y);
assert(cur_rr_node->type == chan_rr_node_type);
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
index d21c62704..4bcbb1921 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
@@ -1252,6 +1252,9 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp,
if (FALSE == is_rr_node_to_be_disable_for_analysis(cur_sb_info->chan_rr_node[side][itrack])) {
continue;
}
+ if (0 == cur_sb_info->chan_rr_node[side][itrack]->fan_in) {
+ continue;
+ }
fprintf(fp, "set_disable_timing ");
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(cur_sb_info));
@@ -1266,6 +1269,9 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp,
if (FALSE == is_rr_node_to_be_disable_for_analysis(cur_sb_info->opin_rr_node[side][inode])) {
continue;
}
+ if (0 == cur_sb_info->opin_rr_node[side][inode]->fan_in) {
+ continue;
+ }
fprintf(fp, "set_disable_timing ");
fprintf(fp, "%s/",
gen_verilog_one_sb_instance_name(cur_sb_info));
@@ -1299,7 +1305,7 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp,
fprintf(fp,
"##################################################\n");
fprintf(fp,
- "### Disable Timing for an %s[%d][%d] ###\n",
+ "### Disable Timing for an unused %s[%d][%d] ###\n",
convert_cb_type_to_string(cur_cb_info->type),
cur_cb_info->x, cur_cb_info->y);
fprintf(fp,
@@ -1320,6 +1326,9 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp,
if (FALSE == is_rr_node_to_be_disable_for_analysis(cur_cb_info->ipin_rr_node[side][inode])) {
continue;
}
+ if (0 == cur_cb_info->ipin_rr_node[side][inode]->fan_in) {
+ continue;
+ }
fprintf(fp, "set_disable_timing ");
fprintf(fp, "%s/",
gen_verilog_one_cb_instance_name(cur_cb_info));
@@ -1586,6 +1595,10 @@ void verilog_generate_sdc_disable_one_unused_block(FILE* fp,
&& (SINK != cur_phy_pb->rr_graph->rr_node[inode].type)) {
continue;
}
+ /* Check if pin is virtual */
+ if (NULL == cur_phy_pb->rr_graph->rr_node[inode].pb_graph_pin) {
+ continue;
+ }
/* Identify if the rr_node is usused */
if (FALSE == is_rr_node_to_be_disable_for_analysis(&(cur_phy_pb->rr_graph->rr_node[inode]))) {
continue;
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c
index a99941eb2..caecf6ebe 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c
@@ -120,7 +120,7 @@ void dump_verilog_one_sb_chan_pin(FILE* fp,
get_rr_node_side_and_index_in_sb_info(cur_rr_node,
*cur_sb_info,
port_type, &side, &track_idx);
- get_chan_rr_node_coorindate_in_sb_info(*cur_sb_info, side,
+ get_chan_rr_node_coordinate_in_sb_info(*cur_sb_info, side,
&(chan_rr_type),
&x_start, &y_start);
assert (chan_rr_type == cur_rr_node->type);
diff --git a/vpr7_x2p/vpr/.regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh
old mode 100755
new mode 100644
similarity index 54%
rename from vpr7_x2p/vpr/.regression_verilog.sh
rename to vpr7_x2p/vpr/regression_verilog.sh
index 75962bf0c..8e777ebca
--- a/vpr7_x2p/vpr/.regression_verilog.sh
+++ b/vpr7_x2p/vpr/regression_verilog.sh
@@ -8,24 +8,10 @@ verilog_output_dirname="${benchmark}_Verilog"
verilog_output_dirpath="$PWD"
modelsim_ini_file="/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini"
# VPR critical inputs
-#set arch_xml_file=ARCH/k6_N10_MD_tsmc40nm_chain_TT.xml
-#set arch_xml_file=ARCH/k8_N10_SC_tsmc40nm_chain_TT_stratixIV_lookalike.xml
-arch_xml_file="ARCH/.travis_k6_N10_sram_chain_HC.xml"
-#set arch_xml_file=ARCH/ed_stdcell.xml
-#set arch_xml_file=ARCH/k6_N10_sram_chain_FC_tsmc40.xml
-#set arch_xml_file=ARCH/k6_N10_SC_tsmc40nm_chain_TT.xml
-#set arch_xml_file=ARCH/k6_N10_SC_tsmc40nm_chain_TT_yosys.xml
-#set arch_xml_file=ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml
-#set verilog_reference=${PWD}/Circuits/alu4_K6_N10_ace.v
-#set blif_file=Circuits/shiftReg.blif
-#set act_file=Circuits/shiftReg.act
-blif_file="Circuits/$benchmark.blif"
-act_file="Circuits/$benchmark.act "
-verilog_reference="${PWD}/Circuits/$benchmark.v"
-#set blif_file=Circuits/frisc.blif
-#set act_file=Circuits/frisc.act
-#set blif_file=Circuits/elliptic.blif
-#set act_file=Circuits/elliptic.act
+arch_xml_file="OPENFPGAPATHKEYWORD/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml"
+blif_file="OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif"
+act_file="OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
+verilog_reference="OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
vpr_route_chan_width="200"
# Step A: Make sure a clean start
@@ -37,7 +23,7 @@ rm -rf $verilog_output_dirpath/$verilog_output_dirname
# Run VPR
#valgrind
-./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties /home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml #--fpga_verilog_print_sdc_analysis --fpga_verilog_print_sdc_pnr
+./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis