diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
index 68d3c9133..7d54c3734 100755
--- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh
+++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
@@ -177,3 +177,7 @@ run-task basic_tests/bus_group/full_testbench_implicit_mapping --debug --show_th
 
 echo -e "Testing fix pins features";
 run-task basic_tests/fix_pins --debug --show_thread_logs
+
+echo -e "Testing project templates";
+run-task template_tasks/vpr_blif_template --debug --show_thread_logs
+run-task template_tasks/yosys_vpr_template --debug --show_thread_logs
diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml
index b045a0c39..0ff0edfd3 100644
--- a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml
+++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml
@@ -7,194 +7,171 @@
        - L = 4, fc_in = 0.15, fc_out = 0.1
   -->
 <openfpga_architecture>
-  <technology_library>
-    <device_library>
-      <device_model name="logic" type="transistor">
-        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="0.9" pn_ratio="2"/>
-        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-      </device_model>
-      <device_model name="io" type="transistor">
-        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="2.5" pn_ratio="3"/>
-        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-      </device_model>
-    </device_library>
-    <variation_library>
-      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-    </variation_library>
-  </technology_library>
-  <circuit_library>
-    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
-      <design_technology type="cmos" topology="inverter" size="1"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
-      <device_technology device_model_name="logic"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
-      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
-      <device_technology device_model_name="logic"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="input" prefix="sel" size="1"/>
-      <port type="input" prefix="selb" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
-        10e-12 5e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
-        10e-12 5e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-    </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-    </circuit_model>
-    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
-    </circuit_model>
-    <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
-      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="--1--"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="6"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="64"/>
-    </circuit_model>
-    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="QN" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
-      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
-      <port type="input" prefix="outpad" lib_name="A" size="1"/>
-      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
-    </circuit_model>
-  </circuit_library>
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="DFFR"/>
-  </configuration_protocol>
-  <connection_block>
-    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
-  </connection_block>
-  <switch_block>
-    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
-  </switch_block>
-  <routing_segment>
-    <segment name="L4" circuit_model_name="chan_segment"/>
-  </routing_segment>
-  <pb_type_annotations>
-    <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
-    <!-- End physical pb_type binding in complex block IO -->
+    <technology_library>
+        <device_library>
+            <device_model name="logic" type="transistor">
+                <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+                <design vdd="0.9" pn_ratio="2"/>
+                <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+                <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+            </device_model>
+            <device_model name="io" type="transistor">
+                <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+                <design vdd="2.5" pn_ratio="3"/>
+                <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+                <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+            </device_model>
+        </device_library>
+        <variation_library>
+            <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+            <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+        </variation_library>
+    </technology_library>
+    <circuit_library>
+        <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+            <design_technology type="cmos" topology="inverter" size="1"/>
+            <device_technology device_model_name="logic"/>
+            <port type="input" prefix="in" size="1"/>
+            <port type="output" prefix="out" size="1"/>
+        </circuit_model>
+        <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+            <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+            <device_technology device_model_name="logic"/>
+            <port type="input" prefix="in" size="1"/>
+            <port type="output" prefix="out" size="1"/>
+        </circuit_model>
+        <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+            <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+            <device_technology device_model_name="logic"/>
+            <port type="input" prefix="in" size="1"/>
+            <port type="output" prefix="out" size="1"/>
+        </circuit_model>
+        <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+            <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+            <device_technology device_model_name="logic"/>
+            <input_buffer exist="false"/>
+            <output_buffer exist="false"/>
+            <port type="input" prefix="in" size="1"/>
+            <port type="input" prefix="sel" size="1"/>
+            <port type="input" prefix="selb" size="1"/>
+            <port type="output" prefix="out" size="1"/>
+        </circuit_model>
+        <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+            <design_technology type="cmos"/>
+            <input_buffer exist="false"/>
+            <output_buffer exist="false"/>
+            <port type="input" prefix="in" size="1"/>
+            <port type="output" prefix="out" size="1"/>
+            <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
+            <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+        </circuit_model>
+        <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+            <design_technology type="cmos"/>
+            <input_buffer exist="false"/>
+            <output_buffer exist="false"/>
+            <port type="input" prefix="in" size="1"/>
+            <port type="output" prefix="out" size="1"/>
+            <wire_param model_type="pi" R="0" C="0" num_level="1"/>
+        </circuit_model>
+        <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+            <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+            <input_buffer exist="true" circuit_model_name="INVTX1"/>
+            <output_buffer exist="true" circuit_model_name="INVTX1"/>
+            <pass_gate_logic circuit_model_name="TGATE"/>
+            <port type="input" prefix="in" size="1"/>
+            <port type="output" prefix="out" size="1"/>
+            <port type="sram" prefix="sram" size="1"/>
+        </circuit_model>
+        <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+            <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+            <input_buffer exist="true" circuit_model_name="INVTX1"/>
+            <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+            <pass_gate_logic circuit_model_name="TGATE"/>
+            <port type="input" prefix="in" size="1"/>
+            <port type="output" prefix="out" size="1"/>
+            <port type="sram" prefix="sram" size="1"/>
+        </circuit_model>
+        <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+            <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+            <input_buffer exist="true" circuit_model_name="INVTX1"/>
+            <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+            <pass_gate_logic circuit_model_name="TGATE"/>
+            <port type="input" prefix="in" size="1"/>
+            <port type="output" prefix="out" size="1"/>
+            <port type="sram" prefix="sram" size="1"/>
+        </circuit_model>
+        <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+        <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
+            <design_technology type="cmos"/>
+            <input_buffer exist="true" circuit_model_name="INVTX1"/>
+            <output_buffer exist="true" circuit_model_name="INVTX1"/>
+            <port type="input" prefix="D" size="1"/>
+            <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+            <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+            <port type="output" prefix="Q" size="1"/>
+            <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+        </circuit_model>
+        <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
+            <design_technology type="cmos"/>
+            <input_buffer exist="true" circuit_model_name="INVTX1"/>
+            <output_buffer exist="true" circuit_model_name="INVTX1"/>
+            <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+            <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+            <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="--1--"/>
+            <pass_gate_logic circuit_model_name="TGATE"/>
+            <port type="input" prefix="in" size="6"/>
+            <port type="output" prefix="out" size="1"/>
+            <port type="sram" prefix="sram" size="64"/>
+        </circuit_model>
+        <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+        <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
+            <design_technology type="cmos"/>
+            <input_buffer exist="true" circuit_model_name="INVTX1"/>
+            <output_buffer exist="true" circuit_model_name="INVTX1"/>
+            <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+            <port type="input" prefix="D" size="1"/>
+            <port type="output" prefix="Q" size="1"/>
+            <port type="output" prefix="QN" size="1"/>
+            <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
+        </circuit_model>
+        <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
+            <design_technology type="cmos"/>
+            <input_buffer exist="true" circuit_model_name="INVTX1"/>
+            <output_buffer exist="true" circuit_model_name="INVTX1"/>
+            <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
+            <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
+            <port type="input" prefix="outpad" lib_name="A" size="1"/>
+            <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+        </circuit_model>
+    </circuit_library>
+    <configuration_protocol>
+        <organization type="scan_chain" circuit_model_name="DFFR"/>
+    </configuration_protocol>
+    <connection_block>
+        <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+    </connection_block>
+    <switch_block>
+        <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+    </switch_block>
+    <routing_segment>
+        <segment name="L4" circuit_model_name="chan_segment"/>
+    </routing_segment>
+    <pb_type_annotations>
+        <!-- physical pb_type binding in complex block IO -->
+        <pb_type name="io" physical_mode_name="physical"/>
+        <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
+        <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
+        <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
+        <!-- End physical pb_type binding in complex block IO -->
 
-    <!-- physical pb_type binding in complex block CLB -->
-    <!-- physical mode will be the default mode if not specified -->
-    <pb_type name="clb">
-      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut6].ble6.lut6" circuit_model_name="lut6"/>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" circuit_model_name="DFFSRQ"/>
-    <!-- End physical pb_type binding in complex block IO -->
-  </pb_type_annotations>
+        <!-- physical pb_type binding in complex block CLB -->
+        <!-- physical mode will be the default mode if not specified -->
+        <pb_type name="clb">
+            <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+            <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+        </pb_type>
+        <pb_type name="clb.fle[n1_lut6].ble6.lut6" circuit_model_name="lut6"/>
+        <pb_type name="clb.fle[n1_lut6].ble6.ff" circuit_model_name="DFFSRQ"/>
+        <!-- End physical pb_type binding in complex block IO -->
+    </pb_type_annotations>
 </openfpga_architecture>
diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml
index a11010a4f..bd76cdcb8 100644
--- a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml
+++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml
@@ -63,25 +63,7 @@
         </auto_layout>
     </layout>
     <device>
-        <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
         <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-        <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	  -->
         <area grid_logic_tile_area="0"/>
         <chan_width_distr>
             <x distr="uniform" peak="1.000000"/>
@@ -91,27 +73,10 @@
         <connection_block input_switch_name="ipin_cblock"/>
     </device>
     <switchlist>
-        <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-	       book area formula. This means the mux transistors are about 5x minimum drive strength.
-	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-	       2.5x when looking up in Jeff's tables.
-	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
         <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-        <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
         <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
     </switchlist>
     <segmentlist>
-        <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
         <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
             <mux name="0"/>
             <sb type="pattern">1 1 1 1 1</sb>
@@ -119,15 +84,9 @@
         </segment>
     </segmentlist>
     <complexblocklist>
-        <!-- Define I/O pads begin -->
-        <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-        <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
         <pb_type name="io">
             <input name="outpad" num_pins="1"/>
             <output name="inpad" num_pins="1"/>
-            <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
             <mode name="physical" disable_packing="true">
                 <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
                     <input name="outpad" num_pins="1"/>
@@ -142,11 +101,6 @@
                     </direct>
                 </interconnect>
             </mode>
-            <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
             <mode name="inpad">
                 <pb_type name="inpad" blif_model=".input" num_pb="1">
                     <output name="inpad" num_pins="1"/>
@@ -167,25 +121,8 @@
                     </direct>
                 </interconnect>
             </mode>
-            <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-            <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-            <!-- Place I/Os on the sides of the FPGA -->
             <power method="ignore"/>
         </pb_type>
-        <!-- Define I/O pads ends -->
-        <!-- Define general purpose logic block (CLB) begin -->
-        <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
         <pb_type name="clb">
             <input name="I" num_pins="40" equivalent="full"/>
             <output name="O" num_pins="10" equivalent="none"/>
@@ -208,23 +145,13 @@
                         <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
                             <input name="in" num_pins="6" port_class="lut_in"/>
                             <output name="out" num_pins="1" port_class="lut_out"/>
-                            <!-- LUT timing using delay matrix -->
-                            <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
                             <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-                261e-12
+                                261e-12
+                                261e-12
+                                261e-12
+                                261e-12
+                                261e-12
+                                261e-12
                             </delay_matrix>
                         </pb_type>
                         <!-- Define flip-flop -->
@@ -258,31 +185,16 @@
                 <!-- 6-LUT mode definition end -->
             </pb_type>
             <interconnect>
-                <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
-		     The delays below come from Stratix IV. the delay through a connection block
-		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-		     delay within the crossbar is 95 ps. 
-		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-		     to get the part that should be marked on the crossbar.	 -->
                 <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
                     <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
                     <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
                 </complete>
                 <complete name="clks" input="clb.clk" output="fle[9:0].clk">
                 </complete>
-                <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-               naive specification).
-          -->
                 <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
             </interconnect>
             <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
             <!-- Place this general purpose logic block in any unspecified column -->
         </pb_type>
-        <!-- Define general purpose logic block (CLB) ends -->
     </complexblocklist>
 </architecture>