From 21a18069a12a4941aab7511b65ae7c4ee252756f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 24 May 2021 14:50:55 -0600 Subject: [PATCH] [Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples --- .../arch_lang/circuit_model_examples.rst | 84 ++++- ...i_mode_dpram128x8_memory_circuit_model.svg | 342 ++++++++++++++++++ ...e_mode_dpram128x8_memory_circuit_model.svg | 104 ++++++ docs/source/overview/tech_highlights.rst | 4 +- 4 files changed, 531 insertions(+), 3 deletions(-) create mode 100644 docs/source/manual/arch_lang/figures/multi_mode_dpram128x8_memory_circuit_model.svg create mode 100644 docs/source/manual/arch_lang/figures/single_mode_dpram128x8_memory_circuit_model.svg diff --git a/docs/source/manual/arch_lang/circuit_model_examples.rst b/docs/source/manual/arch_lang/circuit_model_examples.rst index 32bddd841..ca5c9e419 100644 --- a/docs/source/manual/arch_lang/circuit_model_examples.rst +++ b/docs/source/manual/arch_lang/circuit_model_examples.rst @@ -284,6 +284,8 @@ This example shows: SRAMs ~~~~~ +.. note:: OpenFPGA does not auto-generate any netlist for SRAM cells. Users should define the HDL modeling in external netlists and ensure consistency to physical designs. + Template ```````` @@ -966,6 +968,8 @@ This example shows: Datapath Flip-Flops ~~~~~~~~~~~~~~~~~~~ +.. note:: OpenFPGA does not auto-generate any netlist for datapath flip-flops. Users should define the HDL modeling in external netlists and ensure consistency to physical designs. + Template ```````` @@ -1036,7 +1040,7 @@ Multi-mode Flip-Flop .. _fig_multi_mode_ff_circuit_model: .. figure:: ./figures/multi_mode_ff_circuit_model.svg - :scale: 100% + :scale: 150% :alt: Multi-mode flip-flop example An example of a flip-flop which can be operate in different modes @@ -1062,6 +1066,8 @@ This example shows: Configuration Chain Flip-Flop ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. note:: OpenFPGA does not auto-generate any netlist for configuration chain flip-flops. Users should define the HDL modeling in external netlists and ensure consistency to physical designs. + Template ```````` @@ -1206,6 +1212,8 @@ The code describing this FF is: Hard Logics ~~~~~~~~~~~ +.. note:: OpenFPGA does not auto-generate any netlist for the hard logics. Users should define the HDL modeling in external netlists and ensure consistency to physical designs. + Template ```````` @@ -1248,6 +1256,78 @@ Full Adder +This example shows: + - A 1-bit full adder which is defined in a Verilog netlist ``adder.v`` and a SPICE netlist ``adder.sp`` + - The adder has three 1-bit inputs, i.e., ``a``, ``b`` and ``cin``, and two 2-bit outputs, i.e., ``cout``, ``sumout``. + + +.. _circuit_model_single_mode_dpram_example: + +Dual Port Block RAM +``````````````````` + +.. figure:: ./figures/single_mode_dpram128x8_memory_circuit_model.svg + :scale: 150% + :alt: An example of a dual port block RAM with 128 addresses and 8-bit data width. + + An example of a dual port block RAM with 128 addresses and 8-bit data width. + +The code describing this block RAM is: + +.. code-block:: xml + + + + + + + + + + + + + + +This example shows: + - A 128x8 dual port RAM which is defined in a Verilog netlist ``dpram.v`` and a SPICE netlist ``dpram.sp`` + - The clock port of the RAM is controlled by a global signal (see details about global signal definition in :ref:`annotate_vpr_arch_physical_tile_annotation`). + +.. _circuit_model_multi_mode_dpram_example: + +Multi-mode Dual Port Block RAM +`````````````````````````````` + +.. figure:: ./figures/multi_mode_dpram128x8_memory_circuit_model.svg + :scale: 150% + :alt: An example of a multi-mode dual port block RAM with 128 addresses and 8-bit data width. + + An example of a dual port block RAM which can operate in two modes: 128x8 and 256x4. + +The code describing this block RAM is: + +.. code-block:: xml + + + + + + + + + + + + + + + +This example shows: + - A fracturable dual port RAM which is defined in a Verilog netlist ``frac_dpram.v`` and a SPICE netlist ``frac_dpram.sp`` + - The dual port RAM can operate in two modes: (1) 128 addresses with 8-bit data width; (2) 256 addresses with 4-bit data width + - The clock port of the RAM is controlled by a global signal (see details about global signal definition in :ref:`annotate_vpr_arch_physical_tile_annotation`). + - The mode-selection bit will be generated by a configurable memory outside the flip-flop, which will be implemented by a circuit model ``CCFF`` defined by users (see an example in :ref:`circuit_model_ccff_example`). + Routing Wire Segments ~~~~~~~~~~~~~~~~~~~~~ @@ -1314,6 +1394,8 @@ This example shows I/O pads ~~~~~~~~ +.. note:: OpenFPGA does not auto-generate any netlist for I/O cells. Users should define the HDL modeling in external netlists and ensure consistency to physical designs. + Template ```````` diff --git a/docs/source/manual/arch_lang/figures/multi_mode_dpram128x8_memory_circuit_model.svg b/docs/source/manual/arch_lang/figures/multi_mode_dpram128x8_memory_circuit_model.svg new file mode 100644 index 000000000..ff02de2fc --- /dev/null +++ b/docs/source/manual/arch_lang/figures/multi_mode_dpram128x8_memory_circuit_model.svg @@ -0,0 +1,342 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.5\n2021-05-24 20:15:49 +0000 + + multi_mode_dual_port_bram 1 + + Layer 1 + + + + + + + + + + + + + + + + + + + + + + + clock + + + + + raddr[7:0] + + + + + waddr[7:0] + + + + + wen + + + + + ren + + + + + data_in[7:0] + + + + + data_out[7:0] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + mode + + + + + + + + + + + + + + + + clock + + + + + raddr[6:0] + + + + + waddr[6:0] + + + + + wen + + + + + ren + + + + + data_in[7:0] + + + + + data_out[7:0] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + mode + + + + + + + + ‘1’ + + + + + + + + + + + + + clock + + + + + raddr[7:0] + + + + + waddr[7:0] + + + + + wen + + + + + ren + + + + + data_in[3:0] + + + + + data_out[3:0] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + mode + + + + + + + + ‘0’ + + + + + Operating mode 2: Dual port 256 + x + 4 RAM + + + + + Operating mode 1: Dual port 128x8 RAM + + + + + Schematic: Multi-mode dual port 128x8/256x4 RAM + + + + + + + + + + + + + diff --git a/docs/source/manual/arch_lang/figures/single_mode_dpram128x8_memory_circuit_model.svg b/docs/source/manual/arch_lang/figures/single_mode_dpram128x8_memory_circuit_model.svg new file mode 100644 index 000000000..458155c98 --- /dev/null +++ b/docs/source/manual/arch_lang/figures/single_mode_dpram128x8_memory_circuit_model.svg @@ -0,0 +1,104 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.5\n2021-05-24 19:57:04 +0000 + + single_mode_dual_port_bram + + Layer 1 + + + + + + + + + + + clock + + + + + raddr[6:0] + + + + + waddr[6:0] + + + + + wen + + + + + ren + + + + + data_in[7:0] + + + + + data_out[7:0] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/source/overview/tech_highlights.rst b/docs/source/overview/tech_highlights.rst index c0d71fd15..461be231c 100644 --- a/docs/source/overview/tech_highlights.rst +++ b/docs/source/overview/tech_highlights.rst @@ -50,8 +50,8 @@ Supported Circuit Designs | | | | - :ref:`circuit_model_dff_example` | | | | | - :ref:`circuit_model_multi_mode_ff_example` | | | | | - Single-port Block RAM | -| | | | - Dual-port Block RAM | -| | | | - Multi-mode Block RAM | +| | | | - :ref:`circuit_model_single_mode_dpram_example` | +| | | | - :ref:`circuit_model_multi_mode_dpram_example` | +-----------------+--------------+-----------+-----------------------------------------------------+ | | Arithmetic | No | Yes | - **Any size** | | | Units | | | - Multiplier |