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Merge pull request #836 from lnis-uofu/xmllint 

Format architecture XML files
This commit is contained in:
tangxifan 2022-10-07 13:36:53 -07:00 committed by GitHub
parent 6e2040f678 35869b480a
commit 215d9dfccb
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GPG Key ID: 4AEE18F83AFDEB23
160 changed files with 33453 additions and 32961 deletions
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2
.github/workflows/build.yml vendored
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@ -1,4 +1,4 @@
name: linux_build name: Test
# Run CI on push, PR, and weekly. # Run CI on push, PR, and weekly.

2
.github/workflows/format.yaml vendored
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@ -19,6 +19,8 @@ jobs:
config: config:
- name: "C/C++" - name: "C/C++"
code_type: "-cpp" code_type: "-cpp"
- name: "XML"
code_type: "-xml"
steps: steps:
- name: Cancel previous - name: Cancel previous
uses: styfle/cancel-workflow-action@0.9.1 uses: styfle/cancel-workflow-action@0.9.1

3
.github/workflows/install_dependencies_build.sh vendored
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@ -59,4 +59,5 @@ sudo apt-get install -y \
clang-7 \ clang-7 \
clang-8 \ clang-8 \
clang-10 \ clang-10 \
clang-format-10 clang-format-10 \
libxml2-utils

8
Makefile
View File

@ -42,6 +42,7 @@ endif
# Define executables # Define executables
PYTHON_EXEC ?= python3 PYTHON_EXEC ?= python3
CLANG_FORMAT_EXEC ?= clang-format-10 CLANG_FORMAT_EXEC ?= clang-format-10
XML_FORMAT_EXEC ?= xmllint
# Put it first so that "make" without argument is like "make help". # Put it first so that "make" without argument is like "make help".
export COMMENT_EXTRACT export COMMENT_EXTRACT
@ -75,6 +76,13 @@ format-cpp:
${CLANG_FORMAT_EXEC} --style=file -i $${f} || exit 1; \ ${CLANG_FORMAT_EXEC} --style=file -i $${f} || exit 1; \
done done
format-xml:
# Format all the XML files under this project, excluding submodules
for f in `find openfpga_flow/vpr_arch openfpga_flow/openfpga_arch -iname *.xml`; \
do \
XMLLINT_INDENT=" " && ${XML_FORMAT_EXEC} --format $${f} --output $${f} || exit 1; \
done
clean: clean:
# Remove current build results # Remove current build results
rm -rf ${BUILD_DIR} yosys/install rm -rf ${BUILD_DIR} yosys/install

40
openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4ClkPin_cc_openfpga.xml
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@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -87,7 +88,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -95,7 +97,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -117,14 +120,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -139,13 +142,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -170,7 +173,7 @@
<segment name="L4" circuit_model_name="chan_segment"/> <segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment> </routing_segment>
<tile_annotations> <tile_annotations>
<!-- MUST explicitly define the number of clock bits <!-- MUST explicitly define the number of clock bits
being consistent with physical tile port definition being consistent with physical tile port definition
--> -->
<global_port name="clk0" is_clock="true" default_val="0"> <global_port name="clk0" is_clock="true" default_val="0">
@ -193,7 +196,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4Clk_cc_openfpga.xml
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@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -87,7 +88,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -95,7 +97,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -117,14 +120,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -139,13 +142,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -184,7 +187,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile8Clk_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -87,7 +88,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -95,7 +97,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -117,14 +120,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -139,13 +142,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -184,7 +187,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,13 +141,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -180,7 +183,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,13 +141,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -184,7 +187,6 @@
<pb_type name="io[inpad_registered].ff" physical_pb_type_name="io[physical].ff"/> <pb_type name="io[inpad_registered].ff" physical_pb_type_name="io[physical].ff"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" lib_name="D" size="1"/> <port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,13 +150,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -184,7 +187,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

42
openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,15 +150,15 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAMSR" prefix="SRAMSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAMSR" prefix="SRAMSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -186,7 +189,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAMR" prefix="SRAMR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAMR" prefix="SRAMR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAMRN" prefix="SRAMRN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAMRN" prefix="SRAMRN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RSTN" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RSTN" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAMS" prefix="SRAMS" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAMS" prefix="SRAMS" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAMSN" prefix="SRAMSN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAMSN" prefix="SRAMSN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pSet" lib_name="SETN" size="1" is_global="true" default_val="1" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SETN" size="1" is_global="true" default_val="1" is_set="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_cc_abspath_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,13 +141,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -175,7 +178,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

50
openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgdscffio_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,19 +141,19 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="CFGDSDFFR" prefix="CFGDSDFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="CFGDSDFFR" prefix="CFGDSDFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="SE" size="1" is_global="true" default_val="0"/> <port type="input" prefix="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="config_enable" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/> <port type="input" prefix="config_enable" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="config_done" lib_name="CFG_DONE" size="1" is_global="true" default_val="0" is_config_enable="true"/> <port type="input" prefix="config_done" lib_name="CFG_DONE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="SI" size="1"/> <port type="input" prefix="SI" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="CFGQN" size="1"/> <port type="output" prefix="CFGQN" size="1"/>
<port type="output" prefix="CFGQ" size="1"/> <port type="output" prefix="CFGQ" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO_CFGD" prefix="GPIO_CFGD" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO_CFGD" prefix="GPIO_CFGD" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -182,7 +185,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

48
openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgscff_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,18 +141,18 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="CFGSDFFR" prefix="CFGSDFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="CFGSDFFR" prefix="CFGSDFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="SE" size="1" is_global="true" default_val="0"/> <port type="input" prefix="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="config_enable" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/> <port type="input" prefix="config_enable" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="SI" size="1"/> <port type="input" prefix="SI" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="CFGQN" size="1"/> <port type="output" prefix="CFGQN" size="1"/>
<port type="output" prefix="CFGQ" size="1"/> <port type="output" prefix="CFGQ" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -180,7 +183,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,13 +141,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -175,7 +178,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

42
openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,15 +141,15 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFSR" prefix="DFFSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFSR" prefix="DFFSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -177,7 +180,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,14 +141,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -176,7 +179,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,14 +141,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFRN" prefix="DFFRN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFRN" prefix="DFFRN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RSTN" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RSTN" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -176,7 +179,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,14 +141,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFS" prefix="DFFS" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFS" prefix="DFFS" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -176,7 +179,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,14 +141,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFSN" prefix="DFFSN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFSN" prefix="DFFSN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pSet" lib_name="SETN" size="1" is_global="true" default_val="1" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SETN" size="1" is_global="true" default_val="1" is_set="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -176,7 +179,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

39
openfpga_flow/openfpga_arch/k4_N4_40nm_dsp8reg_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,13 +141,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -183,7 +186,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">
@ -193,7 +195,6 @@
<pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/> <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
<pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/> <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block dsp --> <!-- physical pb_type binding in complex block dsp -->
<pb_type name="mult_8" physical_mode_name="mult_8x8" idle_mode_name="mult_8x8"/> <pb_type name="mult_8" physical_mode_name="mult_8x8" idle_mode_name="mult_8x8"/>
<!-- Bind the primitive pb_type in the physical mode to a circuit model --> <!-- Bind the primitive pb_type in the physical mode to a circuit model -->

40
openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="sram" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="CK" size="1" is_edge_triggered="true"/> <port type="wl" prefix="wl" lib_name="CK" size="1" is_edge_triggered="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_const_input_gnd_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="0"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="0"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,13 +150,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCH" prefix="LATCH" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCH" prefix="LATCH" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -184,7 +187,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_no_const_input_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -80,7 +81,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -88,7 +90,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree"/> <design_technology type="cmos" structure="tree"/>
@ -110,14 +113,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -132,13 +135,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCH" prefix="LATCH" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCH" prefix="LATCH" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -169,7 +172,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,13 +150,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCH" prefix="LATCH" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCH" prefix="LATCH" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -184,7 +187,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

46
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,17 +150,17 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SDFFSR" prefix="SDFFSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="sram" name="SDFFSR" prefix="SDFFSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="CK" size="1" is_edge_triggered="true"/> <port type="wl" prefix="wl" lib_name="CK" size="1" is_edge_triggered="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
<port type="input" prefix="SE" lib_name="SE" size="1" is_global="true" default_val="0"/> <port type="input" prefix="SE" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="SI" lib_name="SI" size="1" is_global="true" default_val="0"/> <port type="input" prefix="SI" lib_name="SI" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -188,7 +191,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

42
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,15 +150,15 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCHSR" prefix="LATCHSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCHSR" prefix="LATCHSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -186,7 +189,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCHRN" prefix="LATCHRN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCHRN" prefix="LATCHRN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RSTN" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RSTN" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCHS" prefix="LATCHS" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCHS" prefix="LATCHS" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCHSN" prefix="LATCHSN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCHSN" prefix="LATCHSN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pSet" lib_name="SETN" size="1" is_global="true" default_val="1" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SETN" size="1" is_global="true" default_val="1" is_set="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" lib_name="D" size="1"/> <port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,13 +150,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -184,7 +187,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

42
openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_use_both_set_reset_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,15 +150,15 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAMSR" prefix="SRAMSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAMSR" prefix="SRAMSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -186,7 +189,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,13 +141,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -175,7 +178,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

42
openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_use_both_set_reset_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -116,14 +119,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -138,15 +141,15 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFSR" prefix="DFFSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFSR" prefix="DFFSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -177,7 +180,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_frame_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,13 +150,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCH" prefix="LATCH" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCH" prefix="LATCH" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -184,7 +187,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

42
openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_frame_use_both_set_reset_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,15 +150,15 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCHSR" prefix="LATCHSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCHSR" prefix="LATCHSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -186,7 +189,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_qlbank_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" lib_name="D" size="1"/> <port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,13 +150,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -184,7 +187,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

72
openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_qlbanksr_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" lib_name="D" size="1"/> <port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,13 +150,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -166,26 +169,26 @@
</circuit_model> </circuit_model>
<!-- The following flip-flop is used to build the shift register chains for configuring memory banks --> <!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
<circuit_model type="ccff" name="BL_DFFRQ" prefix="BL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v" is_default="true"> <circuit_model type="ccff" name="BL_DFFRQ" prefix="BL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" lib_name="SIN" size="1"/> <port type="input" prefix="D" lib_name="SIN" size="1"/>
<port type="output" prefix="Q" lib_name="SOUT" size="1"/> <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
<port type="bl" prefix="BL" lib_name="BL" size="1"/> <port type="bl" prefix="BL" lib_name="BL" size="1"/>
<port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/> <port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
</circuit_model> </circuit_model>
<!-- The following flip-flop is used to build the shift register chains for configuring memory banks --> <!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
<circuit_model type="ccff" name="WL_DFFRQ" prefix="WL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="WL_DFFRQ" prefix="WL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" lib_name="SIN" size="1"/> <port type="input" prefix="D" lib_name="SIN" size="1"/>
<port type="output" prefix="Q" lib_name="SOUT" size="1"/> <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
<port type="wl" prefix="wl" lib_name="WLW" size="1"/> <port type="wl" prefix="wl" lib_name="WLW" size="1"/>
<port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/> <port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
@ -210,7 +213,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -92,7 +93,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -100,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -131,14 +134,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -153,14 +156,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -191,7 +194,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_qlbank_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" lib_name="D" size="1"/> <port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,13 +150,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -184,7 +187,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_qlbank_wlr_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" lib_name="D" size="1"/> <port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAM_RE" prefix="SRAM_RE" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAM_RE" prefix="SRAM_RE" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="wlr" prefix="wlr" lib_name="RE" size="1"/> <port type="wlr" prefix="wlr" lib_name="RE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

38
openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" lib_name="D" size="1"/> <port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,13 +150,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -187,7 +190,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_wlr_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" lib_name="D" size="1"/> <port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAM_RE" prefix="SRAM_RE" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAM_RE" prefix="SRAM_RE" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="wlr" prefix="wlr" lib_name="RE" size="1"/> <port type="wlr" prefix="wlr" lib_name="RE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -188,7 +191,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

72
openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_multi_chain_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" lib_name="D" size="1"/> <port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,13 +150,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -166,26 +169,26 @@
</circuit_model> </circuit_model>
<!-- The following flip-flop is used to build the shift register chains for configuring memory banks --> <!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
<circuit_model type="ccff" name="BL_DFFRQ" prefix="BL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v" is_default="true"> <circuit_model type="ccff" name="BL_DFFRQ" prefix="BL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" lib_name="SIN" size="1"/> <port type="input" prefix="D" lib_name="SIN" size="1"/>
<port type="output" prefix="Q" lib_name="SOUT" size="1"/> <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
<port type="bl" prefix="BL" lib_name="BL" size="1"/> <port type="bl" prefix="BL" lib_name="BL" size="1"/>
<port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/> <port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
</circuit_model> </circuit_model>
<!-- The following flip-flop is used to build the shift register chains for configuring memory banks --> <!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
<circuit_model type="ccff" name="WL_DFFRQ" prefix="WL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="WL_DFFRQ" prefix="WL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" lib_name="SIN" size="1"/> <port type="input" prefix="D" lib_name="SIN" size="1"/>
<port type="output" prefix="Q" lib_name="SOUT" size="1"/> <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
<port type="wl" prefix="wl" lib_name="WLW" size="1"/> <port type="wl" prefix="wl" lib_name="WLW" size="1"/>
<port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/> <port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
@ -210,7 +213,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

72
openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" lib_name="D" size="1"/> <port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,13 +150,13 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -166,26 +169,26 @@
</circuit_model> </circuit_model>
<!-- The following flip-flop is used to build the shift register chains for configuring memory banks --> <!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
<circuit_model type="ccff" name="BL_DFFRQ" prefix="BL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v" is_default="true"> <circuit_model type="ccff" name="BL_DFFRQ" prefix="BL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" lib_name="SIN" size="1"/> <port type="input" prefix="D" lib_name="SIN" size="1"/>
<port type="output" prefix="Q" lib_name="SOUT" size="1"/> <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
<port type="bl" prefix="BL" lib_name="BL" size="1"/> <port type="bl" prefix="BL" lib_name="BL" size="1"/>
<port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/> <port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
</circuit_model> </circuit_model>
<!-- The following flip-flop is used to build the shift register chains for configuring memory banks --> <!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
<circuit_model type="ccff" name="WL_DFFRQ" prefix="WL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="WL_DFFRQ" prefix="WL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" lib_name="SIN" size="1"/> <port type="input" prefix="D" lib_name="SIN" size="1"/>
<port type="output" prefix="Q" lib_name="SOUT" size="1"/> <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
<port type="wl" prefix="wl" lib_name="WLW" size="1"/> <port type="wl" prefix="wl" lib_name="WLW" size="1"/>
<port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/> <port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
@ -210,7 +213,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

76
openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_wlr_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" lib_name="D" size="1"/> <port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="SRAM_RE" prefix="SRAM_RE" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v"> <circuit_model type="sram" name="SRAM_RE" prefix="SRAM_RE" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="wlr" prefix="wlr" lib_name="RE" size="1"/> <port type="wlr" prefix="wlr" lib_name="RE" size="1"/>
<port type="output" prefix="out" lib_name="Q" size="1"/> <port type="output" prefix="out" lib_name="Q" size="1"/>
<port type="output" prefix="outb" lib_name="QN" size="1"/> <port type="output" prefix="outb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -167,27 +170,27 @@
</circuit_model> </circuit_model>
<!-- The following flip-flop is used to build the shift register chains for configuring memory banks --> <!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
<circuit_model type="ccff" name="BL_DFFRQ" prefix="BL_DFFRQ" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="BL_DFFRQ" prefix="BL_DFFRQ" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" lib_name="SIN" size="1"/> <port type="input" prefix="D" lib_name="SIN" size="1"/>
<port type="output" prefix="Q" lib_name="SOUT" size="1"/> <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
<port type="bl" prefix="BL" lib_name="BL" size="1"/> <port type="bl" prefix="BL" lib_name="BL" size="1"/>
<port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/> <port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
</circuit_model> </circuit_model>
<!-- The following flip-flop is used to build the shift register chains for configuring memory banks --> <!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
<circuit_model type="ccff" name="WLR_DFFRQ" prefix="WLR_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="WLR_DFFRQ" prefix="WLR_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" lib_name="SIN" size="1"/> <port type="input" prefix="D" lib_name="SIN" size="1"/>
<port type="output" prefix="Q" lib_name="SOUT" size="1"/> <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
<port type="wl" prefix="wl" lib_name="WLW" size="1"/> <port type="wl" prefix="wl" lib_name="WLW" size="1"/>
<port type="wlr" prefix="wlr" lib_name="WLR" size="1"/> <port type="wlr" prefix="wlr" lib_name="WLR" size="1"/>
<port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/> <port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
@ -212,7 +215,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/> <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>

40
openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_fracNative_N4_40nm_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -150,14 +153,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -188,7 +191,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -203,7 +206,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_abspath_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -217,7 +220,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -217,7 +220,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

41
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -228,7 +231,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">
@ -265,6 +267,5 @@
<!-- physical pb_type binding in complex block memory --> <!-- physical pb_type binding in complex block memory -->
<pb_type name="memory[mem_128x8_dp].mem_128x8_dp" circuit_model_name="dpram_128x8"/> <pb_type name="memory[mem_128x8_dp].mem_128x8_dp" circuit_model_name="dpram_128x8"/>
<!-- END physical pb_type binding in complex block memory --> <!-- END physical pb_type binding in complex block memory -->
</pb_type_annotations> </pb_type_annotations>
</openfpga_architecture> </openfpga_architecture>

41
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -232,7 +235,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">
@ -269,6 +271,5 @@
<!-- physical pb_type binding in complex block memory --> <!-- physical pb_type binding in complex block memory -->
<pb_type name="memory[mem_128x8_dp].mem_128x8_dp" circuit_model_name="dpram_128x8"/> <pb_type name="memory[mem_128x8_dp].mem_128x8_dp" circuit_model_name="dpram_128x8"/>
<!-- END physical pb_type binding in complex block memory --> <!-- END physical pb_type binding in complex block memory -->
</pb_type_annotations> </pb_type_annotations>
</openfpga_architecture> </openfpga_architecture>

41
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v"> <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/latch.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="bl" prefix="bl" lib_name="D" size="1"/> <port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="WE" size="1"/> <port type="wl" prefix="wl" lib_name="WE" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/> <port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/> <port type="output" prefix="Qb" lib_name="QN" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -238,7 +241,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">
@ -275,7 +277,6 @@
<!-- physical pb_type binding in complex block memory --> <!-- physical pb_type binding in complex block memory -->
<pb_type name="memory[mem_128x8_dp].mem_128x8_dp" circuit_model_name="dpram_128x8"/> <pb_type name="memory[mem_128x8_dp].mem_128x8_dp" circuit_model_name="dpram_128x8"/>
<!-- END physical pb_type binding in complex block memory --> <!-- END physical pb_type binding in complex block memory -->
<!-- physical pb_type binding in complex block dsp --> <!-- physical pb_type binding in complex block dsp -->
<pb_type name="mult_32" physical_mode_name="mult_32x32" idle_mode_name="mult_32x32"/> <pb_type name="mult_32" physical_mode_name="mult_32x32" idle_mode_name="mult_32x32"/>
<!-- Bind the primitive pb_type in the physical mode to a circuit model --> <!-- Bind the primitive pb_type in the physical mode to a circuit model -->

40
openfpga_flow/openfpga_arch/k4_frac_N4_fracff2edge_40nm_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="MULTI_MODE_DFFNRQ" prefix="MULTI_MODE_DFFNRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dffn.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="MULTI_MODE_DFFNRQ" prefix="MULTI_MODE_DFFNRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dffn.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="R" lib_name="RST" size="1" default_val="0"/> <port type="input" prefix="R" lib_name="RST" size="1" default_val="0"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="C" lib_name="CK" size="1" default_val="0"/> <port type="clock" prefix="C" lib_name="CK" size="1" default_val="0"/>
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="0"/> <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -211,7 +214,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="MULTI_MODE_DFFRQ" prefix="MULTI_MODE_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="MULTI_MODE_DFFRQ" prefix="MULTI_MODE_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="R" lib_name="RST" size="1" default_val="0"/> <port type="input" prefix="R" lib_name="RST" size="1" default_val="0"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="C" lib_name="CK" size="1" default_val="0"/> <port type="clock" prefix="C" lib_name="CK" size="1" default_val="0"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="0"/> <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -211,7 +214,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_frac_N4_lut_use_and_switch_40nm_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -203,7 +206,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k4_frac_N4_lutram_40nm_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -213,7 +216,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

4
openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k4_frac_cc_sky130nm.xml This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block - General purpose logic block
@ -158,7 +159,7 @@
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -222,7 +223,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>

4
openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k4_frac_cc_sky130nm.xml This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block - General purpose logic block
@ -158,7 +159,7 @@
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -224,7 +225,6 @@
<pb_type name="gp_inpad.inpad" circuit_model_name="GPIN"/> <pb_type name="gp_inpad.inpad" circuit_model_name="GPIN"/>
<pb_type name="gp_outpad.outpad" circuit_model_name="GPOUT"/> <pb_type name="gp_outpad.outpad" circuit_model_name="GPOUT"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>

4
openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k4_frac_cc_sky130nm.xml This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block - General purpose logic block
@ -157,7 +158,7 @@
<port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/> <port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="reset" lib_name="RST" size="1" default_val="0"/> <port type="input" prefix="reset" lib_name="RST" size="1" default_val="0"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -232,7 +233,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>

16
openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k4_frac_cc_sky130nm.xml This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block - General purpose logic block
@ -157,7 +158,7 @@
<port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/> <port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="reset" lib_name="RST" size="1" default_val="0"/> <port type="input" prefix="reset" lib_name="RST" size="1" default_val="0"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4_arith" prefix="frac_lut4_arith" dump_structural_verilog="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v"> <circuit_model type="lut" name="frac_lut4_arith" prefix="frac_lut4_arith" dump_structural_verilog="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -232,12 +233,12 @@
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/> <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
</direct_connection> </direct_connection>
<tile_annotations> <tile_annotations>
<global_port name="clk" is_clock="true" default_val="0"> <global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk" x="-1" y="-1"/> <tile name="clb" port="clk" x="-1" y="-1"/>
</global_port> </global_port>
<global_port name="Reset" is_reset="true" default_val="1"> <global_port name="Reset" is_reset="true" default_val="1">
<tile name="clb" port="reset" x="-1" y="-1"/> <tile name="clb" port="reset" x="-1" y="-1"/>
</global_port> </global_port>
</tile_annotations> </tile_annotations>
<pb_type_annotations> <pb_type_annotations>
<!-- physical pb_type binding in complex block IO --> <!-- physical pb_type binding in complex block IO -->
@ -247,7 +248,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>

16
openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k4_frac_cc_sky130nm.xml This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block - General purpose logic block
@ -157,7 +158,7 @@
<port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/> <port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="reset" lib_name="RST" size="1" default_val="0"/> <port type="input" prefix="reset" lib_name="RST" size="1" default_val="0"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -229,12 +230,12 @@
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/> <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
</direct_connection> </direct_connection>
<tile_annotations> <tile_annotations>
<global_port name="clk" is_clock="true" default_val="0"> <global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk" x="-1" y="-1"/> <tile name="clb" port="clk" x="-1" y="-1"/>
</global_port> </global_port>
<global_port name="Reset" is_reset="true" default_val="1"> <global_port name="Reset" is_reset="true" default_val="1">
<tile name="clb" port="reset" x="-1" y="-1"/> <tile name="clb" port="reset" x="-1" y="-1"/>
</global_port> </global_port>
</tile_annotations> </tile_annotations>
<pb_type_annotations> <pb_type_annotations>
<!-- physical pb_type binding in complex block IO --> <!-- physical pb_type binding in complex block IO -->
@ -244,7 +245,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>

17
openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k4_frac_cc_sky130nm.xml This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block - General purpose logic block
@ -157,7 +158,7 @@
<port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/> <port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="reset" lib_name="RST" size="1" default_val="0"/> <port type="input" prefix="reset" lib_name="RST" size="1" default_val="0"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -237,12 +238,12 @@
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/> <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
</direct_connection> </direct_connection>
<tile_annotations> <tile_annotations>
<global_port name="clk" is_clock="true" default_val="0"> <global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk" x="-1" y="-1"/> <tile name="clb" port="clk" x="-1" y="-1"/>
</global_port> </global_port>
<global_port name="Reset" is_reset="true" default_val="1"> <global_port name="Reset" is_reset="true" default_val="1">
<tile name="clb" port="reset" x="-1" y="-1"/> <tile name="clb" port="reset" x="-1" y="-1"/>
</global_port> </global_port>
</tile_annotations> </tile_annotations>
<pb_type_annotations> <pb_type_annotations>
<!-- physical pb_type binding in complex block IO --> <!-- physical pb_type binding in complex block IO -->
@ -252,7 +253,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
@ -280,7 +280,6 @@
<!-- Binding operating pb_types in mode 'shift_register' --> <!-- Binding operating pb_types in mode 'shift_register' -->
<pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/> <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block dsp --> <!-- physical pb_type binding in complex block dsp -->
<pb_type name="mult_8" physical_mode_name="mult_8x8" idle_mode_name="mult_8x8"/> <pb_type name="mult_8" physical_mode_name="mult_8x8" idle_mode_name="mult_8x8"/>
<!-- Bind the primitive pb_type in the physical mode to a circuit model --> <!-- Bind the primitive pb_type in the physical mode to a circuit model -->

17
openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k4_frac_cc_sky130nm.xml This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block - General purpose logic block
@ -157,7 +158,7 @@
<port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/> <port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="reset" lib_name="RST" size="1" default_val="0"/> <port type="input" prefix="reset" lib_name="RST" size="1" default_val="0"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -238,12 +239,12 @@
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/> <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
</direct_connection> </direct_connection>
<tile_annotations> <tile_annotations>
<global_port name="clk" is_clock="true" default_val="0"> <global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk" x="-1" y="-1"/> <tile name="clb" port="clk" x="-1" y="-1"/>
</global_port> </global_port>
<global_port name="Reset" is_reset="true" default_val="1"> <global_port name="Reset" is_reset="true" default_val="1">
<tile name="clb" port="reset" x="-1" y="-1"/> <tile name="clb" port="reset" x="-1" y="-1"/>
</global_port> </global_port>
</tile_annotations> </tile_annotations>
<pb_type_annotations> <pb_type_annotations>
<!-- physical pb_type binding in complex block IO --> <!-- physical pb_type binding in complex block IO -->
@ -253,7 +254,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
@ -281,7 +281,6 @@
<!-- Binding operating pb_types in mode 'shift_register' --> <!-- Binding operating pb_types in mode 'shift_register' -->
<pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/> <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block dsp --> <!-- physical pb_type binding in complex block dsp -->
<pb_type name="mult_16" physical_mode_name="mult_16x16"/> <pb_type name="mult_16" physical_mode_name="mult_16x16"/>
<!-- Bind the primitive pb_type in the physical mode to a circuit model --> <!-- Bind the primitive pb_type in the physical mode to a circuit model -->

40
openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -147,14 +150,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -185,7 +188,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -86,7 +87,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -94,7 +96,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -125,14 +128,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -148,14 +151,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -186,7 +189,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -203,7 +206,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -166,14 +169,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -217,7 +220,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

42
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -166,14 +169,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -239,7 +242,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">
@ -274,12 +276,10 @@
</pb_type> </pb_type>
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/> <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- End physical pb_type binding in complex block clb --> <!-- End physical pb_type binding in complex block clb -->
<!-- physical pb_type binding in complex block dsp --> <!-- physical pb_type binding in complex block dsp -->
<pb_type name="mult_36" physical_mode_name="mult_36x36" idle_mode_name="mult_36x36"/> <pb_type name="mult_36" physical_mode_name="mult_36x36" idle_mode_name="mult_36x36"/>
<!-- Bind the primitive pb_type in the physical mode to a circuit model --> <!-- Bind the primitive pb_type in the physical mode to a circuit model -->
<pb_type name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" circuit_model_name="mult_36x36" mode_bits="00"/> <pb_type name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" circuit_model_name="mult_36x36" mode_bits="00"/>
<!-- physical pb_type binding in complex block memory --> <!-- physical pb_type binding in complex block memory -->
<pb_type name="memory[mem_1024x8_dp].mem_1024x8_dp" circuit_model_name="dpram_1024x8"/> <pb_type name="memory[mem_1024x8_dp].mem_1024x8_dp" circuit_model_name="dpram_1024x8"/>
<!-- END physical pb_type binding in complex block memory --> <!-- END physical pb_type binding in complex block memory -->

44
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,15 +143,15 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="MULTI_MODE_DFFSRQ" prefix="MULTI_MODE_DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="MULTI_MODE_DFFSRQ" prefix="MULTI_MODE_DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="S" lib_name="SET" size="1"/> <port type="input" prefix="S" lib_name="SET" size="1"/>
<port type="input" prefix="R" lib_name="RST" size="1"/> <port type="input" prefix="R" lib_name="RST" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="C" lib_name="CK" size="1"/> <port type="clock" prefix="C" lib_name="CK" size="1"/>
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="0"/> <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -167,14 +170,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -252,7 +255,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">
@ -320,12 +322,10 @@
<port name="SN" physical_mode_port="S"/> <port name="SN" physical_mode_port="S"/>
</pb_type> </pb_type>
<!-- End physical pb_type binding in complex block clb --> <!-- End physical pb_type binding in complex block clb -->
<!-- physical pb_type binding in complex block dsp --> <!-- physical pb_type binding in complex block dsp -->
<pb_type name="mult_36" physical_mode_name="mult_36x36" idle_mode_name="mult_36x36"/> <pb_type name="mult_36" physical_mode_name="mult_36x36" idle_mode_name="mult_36x36"/>
<!-- Bind the primitive pb_type in the physical mode to a circuit model --> <!-- Bind the primitive pb_type in the physical mode to a circuit model -->
<pb_type name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" circuit_model_name="mult_36x36" mode_bits="00"/> <pb_type name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" circuit_model_name="mult_36x36" mode_bits="00"/>
<!-- physical pb_type binding in complex block memory --> <!-- physical pb_type binding in complex block memory -->
<pb_type name="memory[mem_1024x8_dp].mem_1024x8_dp" circuit_model_name="dpram_1024x8"/> <pb_type name="memory[mem_1024x8_dp].mem_1024x8_dp" circuit_model_name="dpram_1024x8"/>
<!-- END physical pb_type binding in complex block memory --> <!-- END physical pb_type binding in complex block memory -->

42
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -166,14 +169,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -252,7 +255,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">
@ -287,7 +289,6 @@
</pb_type> </pb_type>
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/> <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- End physical pb_type binding in complex block clb --> <!-- End physical pb_type binding in complex block clb -->
<!-- physical pb_type binding in complex block dsp --> <!-- physical pb_type binding in complex block dsp -->
<pb_type name="mult_36" physical_mode_name="mult_36x36" idle_mode_name="mult_36x36"/> <pb_type name="mult_36" physical_mode_name="mult_36x36" idle_mode_name="mult_36x36"/>
<!-- Bind the primitive pb_type in the physical mode to a circuit model --> <!-- Bind the primitive pb_type in the physical mode to a circuit model -->
@ -311,7 +312,6 @@
<port name="out" physical_mode_port="out[0:35]" physical_mode_pin_rotate_offset="36"/> <port name="out" physical_mode_port="out[0:35]" physical_mode_pin_rotate_offset="36"/>
</pb_type> </pb_type>
<!-- END physical pb_type binding in complex block dsp --> <!-- END physical pb_type binding in complex block dsp -->
<!-- physical pb_type binding in complex block memory --> <!-- physical pb_type binding in complex block memory -->
<pb_type name="memory" physical_mode_name="physical" idle_mode_name="physical"/> <pb_type name="memory" physical_mode_name="physical" idle_mode_name="physical"/>
<pb_type name="memory[physical].frac_mem_32k" circuit_model_name="frac_mem_32k" mode_bits="0000"/> <pb_type name="memory[physical].frac_mem_32k" circuit_model_name="frac_mem_32k" mode_bits="0000"/>

42
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -166,14 +169,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -243,7 +246,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">
@ -278,7 +280,6 @@
</pb_type> </pb_type>
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/> <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- End physical pb_type binding in complex block clb --> <!-- End physical pb_type binding in complex block clb -->
<!-- physical pb_type binding in complex block dsp --> <!-- physical pb_type binding in complex block dsp -->
<pb_type name="mult_36" physical_mode_name="mult_36x36" idle_mode_name="mult_36x36"/> <pb_type name="mult_36" physical_mode_name="mult_36x36" idle_mode_name="mult_36x36"/>
<!-- Bind the primitive pb_type in the physical mode to a circuit model --> <!-- Bind the primitive pb_type in the physical mode to a circuit model -->
@ -302,7 +303,6 @@
<port name="out" physical_mode_port="out[0:35]" physical_mode_port_rotate_offset="36"/> <port name="out" physical_mode_port="out[0:35]" physical_mode_port_rotate_offset="36"/>
</pb_type> </pb_type>
<!-- END physical pb_type binding in complex block dsp --> <!-- END physical pb_type binding in complex block dsp -->
<!-- physical pb_type binding in complex block memory --> <!-- physical pb_type binding in complex block memory -->
<pb_type name="memory" physical_mode_name="physical" idle_mode_name="physical"/> <pb_type name="memory" physical_mode_name="physical" idle_mode_name="physical"/>
<pb_type name="memory[physical].frac_mem_32k" circuit_model_name="frac_mem_32k" mode_bits="0000"/> <pb_type name="memory[physical].frac_mem_32k" circuit_model_name="frac_mem_32k" mode_bits="0000"/>

42
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -166,14 +169,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -229,7 +232,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">
@ -264,8 +266,6 @@
</pb_type> </pb_type>
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/> <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- End physical pb_type binding in complex block clb --> <!-- End physical pb_type binding in complex block clb -->
<!-- physical pb_type binding in complex block memory --> <!-- physical pb_type binding in complex block memory -->
<pb_type name="memory[mem_512x32_dp].mem_512x32_dp" circuit_model_name="dpram_512x32"/> <pb_type name="memory[mem_512x32_dp].mem_512x32_dp" circuit_model_name="dpram_512x32"/>
<!-- END physical pb_type binding in complex block memory --> <!-- END physical pb_type binding in complex block memory -->

42
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -166,14 +169,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -241,7 +244,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">
@ -276,8 +278,6 @@
</pb_type> </pb_type>
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/> <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- End physical pb_type binding in complex block clb --> <!-- End physical pb_type binding in complex block clb -->
<!-- physical pb_type binding in complex block memory --> <!-- physical pb_type binding in complex block memory -->
<pb_type name="memory[mem_512x32_dp].mem_512x32_dp" circuit_model_name="dpram_512x32"/> <pb_type name="memory[mem_512x32_dp].mem_512x32_dp" circuit_model_name="dpram_512x32"/>
<!-- END physical pb_type binding in complex block memory --> <!-- END physical pb_type binding in complex block memory -->

42
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1"/> <port type="clock" prefix="clk" lib_name="CK" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -166,14 +169,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -235,7 +238,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">
@ -270,8 +272,6 @@
</pb_type> </pb_type>
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/> <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<!-- End physical pb_type binding in complex block clb --> <!-- End physical pb_type binding in complex block clb -->
<!-- physical pb_type binding in complex block memory --> <!-- physical pb_type binding in complex block memory -->
<pb_type name="memory[mem_128x8_dp].mem_128x8_dp" circuit_model_name="dpram_128x8"/> <pb_type name="memory[mem_128x8_dp].mem_128x8_dp" circuit_model_name="dpram_128x8"/>
<!-- END physical pb_type binding in complex block memory --> <!-- END physical pb_type binding in complex block memory -->

40
openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -166,14 +169,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -217,7 +220,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -166,14 +169,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -218,7 +221,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

44
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -143,16 +146,16 @@
When the TESTEN is enabled, the data will be propagated form DI instead of D When the TESTEN is enabled, the data will be propagated form DI instead of D
--> -->
<circuit_model type="ff" name="SDFFSRQ" prefix="SDFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="SDFFSRQ" prefix="SDFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="DI" lib_name="SI" size="1"/> <port type="input" prefix="DI" lib_name="SI" size="1"/>
<port type="input" prefix="TESTEN" lib_name="SE" size="1" is_global="true" default_val="0"/> <port type="input" prefix="TESTEN" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -171,14 +174,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -224,7 +227,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

44
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -143,16 +146,16 @@
When the TESTEN is enabled, the data will be propagated form DI instead of D When the TESTEN is enabled, the data will be propagated form DI instead of D
--> -->
<circuit_model type="ff" name="SDFFSRQ" prefix="SDFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="SDFFSRQ" prefix="SDFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="D_chain" lib_name="SI" size="1"/> <port type="input" prefix="D_chain" lib_name="SI" size="1"/>
<port type="input" prefix="TESTEN" lib_name="SE" size="1" is_global="true" default_val="0"/> <port type="input" prefix="TESTEN" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -171,14 +174,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -223,7 +226,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>

49
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -143,16 +146,16 @@
When the TESTEN is enabled, the data will be propagated form DI instead of D When the TESTEN is enabled, the data will be propagated form DI instead of D
--> -->
<circuit_model type="ff" name="SDFFSRQ" prefix="SDFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="SDFFSRQ" prefix="SDFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="D_chain" lib_name="SI" size="1"/> <port type="input" prefix="D_chain" lib_name="SI" size="1"/>
<port type="input" prefix="TESTEN" lib_name="SE" size="1" is_global="true" default_val="0"/> <port type="input" prefix="TESTEN" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" is_default="true" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -186,14 +189,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -238,7 +241,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
@ -271,11 +273,9 @@
<!-- Binding operating pb_types in mode 'shift_register' --> <!-- Binding operating pb_types in mode 'shift_register' -->
<pb_type name="clb.fle[shift_register].ble_shift.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/> <pb_type name="clb.fle[shift_register].ble_shift.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/>
<!-- End physical pb_type binding in complex block CLB --> <!-- End physical pb_type binding in complex block CLB -->
<!-- physical pb_type binding in complex block CLB with spypads--> <!-- physical pb_type binding in complex block CLB with spypads-->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb_spypad.fle" physical_mode_name="physical"/> <pb_type name="clb_spypad.fle" physical_mode_name="physical"/>
<!-- Binding regular FLEs --> <!-- Binding regular FLEs -->
<pb_type name="clb_spypad.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/> <pb_type name="clb_spypad.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/>
<pb_type name="clb_spypad.fle[physical].ff_phy" circuit_model_name="SDFFSRQ"/> <pb_type name="clb_spypad.fle[physical].ff_phy" circuit_model_name="SDFFSRQ"/>
@ -305,11 +305,9 @@
<pb_type name="clb_spypad.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb_spypad.fle[physical].ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/> <pb_type name="clb_spypad.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb_spypad.fle[physical].ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
<!-- Binding operating pb_types in mode 'shift_register' --> <!-- Binding operating pb_types in mode 'shift_register' -->
<pb_type name="clb_spypad.fle[shift_register].ble_shift.ff" physical_pb_type_name="clb_spypad.fle[physical].ff_phy"/> <pb_type name="clb_spypad.fle[shift_register].ble_shift.ff" physical_pb_type_name="clb_spypad.fle[physical].ff_phy"/>
<!-- Binding FLE with spy pads --> <!-- Binding FLE with spy pads -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb_spypad.fle_spypad" physical_mode_name="physical"/> <pb_type name="clb_spypad.fle_spypad" physical_mode_name="physical"/>
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6_spypad" mode_bits="00"/> <pb_type name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6_spypad" mode_bits="00"/>
<pb_type name="clb_spypad.fle_spypad[physical].ff_phy" circuit_model_name="SDFFSRQ"/> <pb_type name="clb_spypad.fle_spypad[physical].ff_phy" circuit_model_name="SDFFSRQ"/>
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.adder_phy" circuit_model_name="ADDF"/> <pb_type name="clb_spypad.fle_spypad[physical].frac_logic.adder_phy" circuit_model_name="ADDF"/>
@ -339,6 +337,5 @@
<!-- Binding operating pb_types in mode 'shift_register' --> <!-- Binding operating pb_types in mode 'shift_register' -->
<pb_type name="clb_spypad.fle_spypad[shift_register].ble_shift.ff" physical_pb_type_name="clb_spypad.fle_spypad[physical].ff_phy"/> <pb_type name="clb_spypad.fle_spypad[shift_register].ble_shift.ff" physical_pb_type_name="clb_spypad.fle_spypad[physical].ff_phy"/>
<!-- End physical pb_type binding in complex block CLB with spypads--> <!-- End physical pb_type binding in complex block CLB with spypads-->
</pb_type_annotations> </pb_type_annotations>
</openfpga_architecture> </openfpga_architecture>

40
openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -203,7 +206,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -203,7 +206,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

42
openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
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@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,20 +168,20 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" /> <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
<!-- A spypad for the direction port of the I/O pad, which can be visible in the fpga_top --> <!-- A spypad for the direction port of the I/O pad, which can be visible in the fpga_top -->
<port type="input" prefix="din" size="1" is_global="true" is_io="true" default_value="0"/> <port type="input" prefix="din" size="1" is_global="true" is_io="true" default_value="0"/>
<port type="output" prefix="dout" size="1" is_global="true" is_io="true"/> <port type="output" prefix="dout" size="1" is_global="true" is_io="true"/>
@ -207,7 +210,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
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@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -102,7 +103,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -110,7 +112,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -132,14 +135,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -157,14 +160,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -195,7 +198,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
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@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -102,7 +103,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -110,7 +112,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -132,14 +135,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -157,14 +160,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -195,7 +198,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
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@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
@ -131,14 +134,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -156,14 +159,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -194,7 +197,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

34
openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N8_40nm.xml This annotation supports the k6_N8_40nm.xml
- General purpose logic block - General purpose logic block
@ -143,14 +144,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -168,14 +169,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -206,7 +207,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N8_40nm.xml This annotation supports the k6_N8_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -203,7 +206,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N8_40nm.xml This annotation supports the k6_N8_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -203,7 +206,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N10_40nm.xml This annotation supports the k6_N10_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -203,7 +206,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

40
openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml
View File

@ -1,3 +1,4 @@
<?xml version="1.0"?>
<!-- Architecture annotation for OpenFPGA framework <!-- Architecture annotation for OpenFPGA framework
This annotation supports the k6_N8_40nm.xml This annotation supports the k6_N8_40nm.xml
- General purpose logic block - General purpose logic block
@ -101,7 +102,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model> </circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -109,7 +111,8 @@
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> <wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model> </circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
@ -140,14 +143,14 @@
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true"> <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/> <design_technology type="cmos" fracturable_lut="true"/>
@ -165,14 +168,14 @@
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/> <port type="output" prefix="QN" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -203,7 +206,6 @@
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb"> <pb_type name="clb">

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