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Correct preconfiguration

This commit is contained in:
AurelienUoU 2019-01-31 16:43:47 -07:00
parent 5e36aa82c5
commit 213f94ddee
1 changed files with 1 additions and 1 deletions
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2
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c
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@ -694,7 +694,7 @@ void dump_verilog_top_preconf_testbench_stimuli(FILE* fp,
fprintf(fp, " for(count = %d; count > -1 ; count = count - 1) begin\n", (num_scffs - 1));
fprintf(fp, " tmp[count] = $fgetc(file);\n");
fprintf(fp, " end\n");
fprintf(fp, " $signal_force(\"U0/%s_scff_in\", tmp, 0, 1, , 1);\n", scff_mem_model->prefix );
fprintf(fp, " $signal_force(\"U0/%s_scff_out\", tmp, 0, 1, , 1);\n", scff_mem_model->prefix );
fprintf(fp, " $fclose(file);\n");
fprintf(fp, "end\n");
fprintf(fp, " // End loading configuration as initial state\n\n");