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[test] add a new testcase to validate dump waveform

This commit is contained in:
tangxifan 2024-03-29 11:53:55 -07:00
parent 6a5d3c7cdc
commit 20386945bd
5 changed files with 41 additions and 1 deletions
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2
openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga
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@ -65,7 +65,7 @@ write_fabric_verilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --inc
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --no_time_stamp write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --no_time_stamp ${OPENFPGA_PRECONFIG_FABRIC_WRAPPER_DUMP_WAVEFORM}
write_preconfigured_testbench --file ${OPENFPGA_OUTPUT_DIR} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --use_relative_path --explicit_port_mapping --no_time_stamp write_preconfigured_testbench --file ${OPENFPGA_OUTPUT_DIR} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --use_relative_path --explicit_port_mapping --no_time_stamp
# Write the SDC files for PnR backend # Write the SDC files for PnR backend

1
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/config/task.conf
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@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
openfpga_vpr_device_layout = auto openfpga_vpr_device_layout = auto
openfpga_vpr_route_chan_width = 26 openfpga_vpr_route_chan_width = 26
openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp
openfpga_preconfig_fabric_wrapper_dump_waveform=
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml

1
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/config/task.conf
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@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
openfpga_vpr_device_layout = 4x4 openfpga_vpr_device_layout = 4x4
openfpga_vpr_route_chan_width = 20 openfpga_vpr_route_chan_width = 20
openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp
openfpga_preconfig_fabric_wrapper_dump_waveform=
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml

37
openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/config/task.conf Normal file
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@ -0,0 +1,37 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_abspath_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout = auto
openfpga_vpr_route_chan_width = 26
openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp
openfpga_preconfig_fabric_wrapper_dump_waveform=--dump_waveform
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

1
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/config/task.conf
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@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
openfpga_vpr_device_layout = 2x2 openfpga_vpr_device_layout = 2x2
openfpga_vpr_route_chan_width = 20 openfpga_vpr_route_chan_width = 20
openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp
openfpga_preconfig_fabric_wrapper_dump_waveform=
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml